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    • 1. 发明申请
    • METHOD OF MANUFACTURING AN ELECTRONIC DEVICE COMPRISING THIN-FILM TRANSISTORS
    • 制造包含薄膜晶体管的电子器件的方法
    • WO9749125A3
    • 1999-11-04
    • PCT/IB9700471
    • 1997-04-30
    • PHILIPS ELECTRONICS NVPHILIPS NORDEN AB
    • YOUNG NIGEL DAVID
    • H01L21/20H01L21/336H01L29/786H01L21/263H01L21/268
    • H01L29/66757H01L21/2026H01L27/1229H01L27/1281H01L29/78609
    • A flat panel display or other large-area electronic device comprises at least one TFT (T1; T2) having a crystalline channel region (1) and amorphous edge regions (13) adjacent sidewalls (12) of the TFT island (11). The TFT is fabricated by steps which include: (a) depositing on substrate (10) a thin film (11') of amorphous semiconductor material to provide the semiconductor material, (b) removing areas of the thin film (11') to form the side walls (12a, 12b) of each island (11), (c) forming a masking pattern (20) over the edge regions (13a, 13b) preferably on an insulating film (22), and (d) directing a laser or other energy beam (50) towards the islands (11) and the masking pattern (20) to crystallise the un-masked semiconductor material for the crystalline channel region (1), while retaining amorphous semiconductor material adjacent the side walls (12a, 12b) where the edge regions (13a, 13b) are masked from the energy beam (50) by the masking pattern (20). The resulting device structure has e.g polycrystalline TFTs (T1, T2) with low off-state leakage currents as a result of the amorphous material properties kept for the edge regions (13a) particularly where crossed by the insulated gate (4). The substrate (10) may be of polymer material which also is masked from the beam (50) by the masking pattern (20).
    • 平板显示器或其他大面积电子器件包括具有晶体沟道区域(1)的至少一个TFT(T1; T2)和与TFT岛(11)的侧壁(12)相邻的非晶边缘区域(13)。 TFT由以下步骤制造,其包括:(a)在衬底(10)上沉积非晶半导体材料的薄膜(11')以提供半导体材料,(b)去除薄膜(11')的区域以形成 每个岛(11)的侧壁(12a,12b),(c)优选地在绝缘膜(22)上在边缘区域(13a,13b)上形成掩模图案(20),和(d)引导激光 或其他能量束(50)朝向岛(11)和掩模图案(20)以结晶用于晶体沟道区域(1)的未掩蔽的半导体材料,同时保持邻近侧壁(12a,12b)的非晶半导体材料 ),其中所述边缘区域(13a,13b)被所述掩模图案(20)从所述能量束(50)掩蔽。 所得到的器件结构具有例如由于对于边缘区域(13a)保持的非晶材料特性,特别是在被绝缘栅极(4)交叉的情况下,具有低截止状态漏电流的多晶硅(T1,T2)。 衬底(10)可以是聚合物材料,其也通过掩模图案(20)从光束(50)掩蔽。
    • 5. 发明申请
    • CAPACITIVE SENSING ARRAY DEVICE
    • 电容式感应阵列装置
    • WO9803934A3
    • 1998-03-19
    • PCT/IB9700878
    • 1997-07-15
    • PHILIPS ELECTRONICS NVPHILIPS NORDEN AB
    • YOUNG NIGEL DAVID
    • A61B5/117G01B7/28G06F3/033G06F3/044G06K11/06
    • G06F3/044
    • A capacitive sensing array device, such as a fingerprint sensing device, comprises an array of individual sensing electrodes (14) covered by a layer of insulating material (40) defining surface on which a person's finger is placed, each sensing electrode, its overlying fingerprint portion and intervening insulating layer providing a capacitance in operation. The sensing electrodes are of chromium and the covering insulating material comprises a thin layer of chromium oxide which offers excellent scratch resistance and can be formed conveniently by oxidation of a surface region of the sensing electrodes. In a row and column array, address lines (18) extending between rows of electrodes (14) may also comprise chromium and be covered by chromium oxide. Preferably, the sensing electrodes and address lines are defined from a common deposited chromium layer. 00000
    • 诸如指纹感测装置的电容式感测阵列装置包括由限定了人的手指放置在其上的绝缘材料层(40)覆盖的各个感测电极(14)的阵列,每个感测电极,其上覆的指纹 部分和中间绝缘层在操作中提供电容。 检测电极为铬,覆盖绝缘材料包括薄层的氧化铬,其提供优异的耐擦伤性,并且可以通过感测电极的表面区域的氧化方便地形成。 在行和列阵列中,在电极(14)的行之间延伸的地址线(18)还可以包括铬并被氧化铬覆盖。 优选地,感测电极和地址线由公共沉积的铬层限定。 00000