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    • 72. 发明授权
    • Electrostatic discharge power clamp trigger circuit using low stress voltage devices
    • 静电放电电源钳位触发电路采用低应力电压器件
    • US08102632B2
    • 2012-01-24
    • US12406684
    • 2009-03-18
    • Yikai LiangArvind BomdicaSamudyatha SuryanarayanaGayatri GopalanMin XuXin LiuMing-Ju Edward Lee
    • Yikai LiangArvind BomdicaSamudyatha SuryanarayanaGayatri GopalanMin XuXin LiuMing-Ju Edward Lee
    • H02H9/00H01C7/12H02H1/00H02H1/04H02H3/22H02H9/06
    • H03K19/00315
    • Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin interface, a voltage drop network coupled to the IO pin and comprising a plurality of forward-biased diodes connected in series to drop a high voltage on the IO pin to a low voltage level, an NMOS shunt transistor coupled between the voltage drop network and a ground terminal, and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time.
    • 描述了保护IC内的低压电源晶体管和电路免受过多电源电平和ESD事件的IC保护电路的实施例。 位于IC的IO引脚和IC内部电路之间的保护电路包括一个压降网络和多个分流电路,以保护IC免受过多的电源电压和ESD电压的影响。 每个并联电路包括使用低电压器件制造的RC触发级和NMOS分流级。 实施例的保护电路包括高电压IO引脚接口,耦合到IO引脚的电压降网络,并且包括串联连接的多个正向偏置二极管以将IO引脚上的高电压降低到低电压电平, 耦合在所述电压降网络和接地端子之间的NMOS分流晶体管,以及耦合到所述NMOS分流晶体管的触发电路,以在感测到的输入电压上升时间短于限定的电源电压上升时间时激活所述并联晶体管。
    • 73. 发明申请
    • METHOD FOR ENTERING AN IDLE MODE
    • 进入空闲模式的方法
    • US20110188426A1
    • 2011-08-04
    • US13054897
    • 2008-12-19
    • Jianquan SongXin LiuLi ChuHongyun QuLing Xu
    • Jianquan SongXin LiuLi ChuHongyun QuLing Xu
    • H04W52/02
    • H04W12/06H04W60/00H04W68/00H04W76/27
    • A method for entering an idle mode, which is used in a Worldwide Interoperability for Microwave Access system, comprising: during the procedure of a terminal enter to idle mode from active mode, an paging agent of the terminal sending mobility restriction parameters of the terminal to a mobility restriction parameter storage network element; the mobility restriction parameter storage network element saving the mobility restriction parameters; the mobility restriction parameter storage network element being an anchor paging controller, or an anchor authenticator, or a function entity including a function of the anchor paging controller and a function of the anchor authenticator. to save the mobility restriction parameters of a terminal when the terminal enters an idle mode may be achieved by using the method of the present invention, so that a mobility restriction judgment is performed to the terminal in the subsequent process procedure, and the problem of erroneously allowing the terminal to quit from the idle mode and enter an active mode or to update its location when the terminal is in the non-authorized regions can be avoided.
    • 一种在全球互通微波接入系统中使用的进入空闲模式的方法,包括:在终端进入空闲模式的过程中,终端的寻呼机发送终端的移动性限制参数, 移动性限制参数存储网元; 移动限制参数存储网元保存移动性限制参数; 移动性限制参数存储网元作为主寻呼控制器,或锚定认证器,或者包括锚寻呼控制器的功能的功能实体和锚定认证器的功能。 当终端进入空闲模式时,为了节省终端的移动性限制参数,可以通过使用本发明的方法来实现,从而在随后的处理过程中对终端执行移动性限制判断,并且存在错误的问题 允许终端从空闲模式退出并进入活动模式或者当终端在非授权区域时可以更新其位置。
    • 74. 发明申请
    • METHOD FOR MEASURING PHASE LOCKED LOOP BANDWIDTH PARAMETERS FOR HIGH-SPEED SERIAL LINKS
    • 用于测量高速串行链路的相位锁定环带宽度参数的方法
    • US20100246739A1
    • 2010-09-30
    • US12410413
    • 2009-03-24
    • Dongming LouPengfei HuJunqiang ShangXin Liu
    • Dongming LouPengfei HuJunqiang ShangXin Liu
    • H04L7/00
    • H03L7/08H04L7/033
    • A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator, determining a reference jitter amplitude value of a clock output of the phase locked loop with a waveform analyzer at the reference frequency, the reference jitter amplitude value being a function of a time interval error jitter trend of the clock output at the reference frequency; and adjusting the jitter frequency of the clock input with the frequency generator until an adjusted jitter amplitude value of the clock output reaches a goal value as determined by the waveform analyzer, the adjusted jitter amplitude being a function of a time interval error trend of the clock output at the adjusted frequency.
    • 一种用于测量高速串行链路的锁相环带宽参数的方法包括以下步骤:利用频率发生器启动等于参考频率的锁相环的时钟输入的抖动频率,确定参考抖动振幅值 基准频率下的波形分析器的锁相环的时钟输出,参考抖动幅度值是参考频率时钟输出的时间间隔误差抖动趋势的函数; 并且通过频率发生器调整时钟输入的抖动频率,直到时钟输出的经调整的抖动幅度值达到由波形分析器确定的目标值,调整后的抖动幅度是时钟的时间间隔误差趋势的函数 以调整频率输出。
    • 76. 发明申请
    • Electrostatic Discharge Power Clamp Trigger Circuit Using Low Stress Voltage Devices
    • 使用低应力电压器件的静电放电电源钳位触发电路
    • US20100238598A1
    • 2010-09-23
    • US12406684
    • 2009-03-18
    • Yikai LiangArvind BomdicaSamudyatha SuryanarayanaGayatri GopalanMin XuXin LiuMing-Ju Edward Lee
    • Yikai LiangArvind BomdicaSamudyatha SuryanarayanaGayatri GopalanMin XuXin LiuMing-Ju Edward Lee
    • H02H9/04G06F17/00
    • H03K19/00315
    • Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin interface, a voltage drop network coupled to the IO pin and comprising a plurality of forward-biased diodes connected in series to drop a high voltage on the IO pin to a low voltage level, an NMOS shunt transistor coupled between the voltage drop network and a ground terminal, and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time.
    • 描述了保护IC内的低压电源晶体管和电路免受过多电源电平和ESD事件的IC保护电路的实施例。 位于IC的IO引脚和IC内部电路之间的保护电路包括一个压降网络和多个分流电路,以保护IC免受过多的电源电压和ESD电压的影响。 每个并联电路包括使用低电压器件制造的RC触发级和NMOS分流级。 实施例的保护电路包括高电压IO引脚接口,耦合到IO引脚的电压降网络,并且包括串联连接的多个正向偏置二极管以将IO引脚上的高电压降低到低电压电平, 耦合在所述电压降网络和接地端子之间的NMOS分流晶体管,以及耦合到所述NMOS分流晶体管的触发电路,以在感测到的输入电压上升时间短于限定的电源电压上升时间时激活所述并联晶体管。
    • 78. 发明申请
    • Ruggedized Fiber Optic Connector Assembly
    • 坚固的光纤连接器组件
    • US20090310916A1
    • 2009-12-17
    • US12534796
    • 2009-08-03
    • James P. LutherThomas TheuerkornXin Liu
    • James P. LutherThomas TheuerkornXin Liu
    • G02B6/38G02B6/00
    • G02B6/3869G02B6/3887
    • A ruggedized fiber optic connector assembly includes a substantially hollow plug housing; and a glue body disposed within the substantially hollow plug housing; wherein the glue body includes a first portion that is configured to engage and retain an optical cable comprising an optical fiber and one or more strength members; wherein the glue body includes a second portion that is configured to engage and retain a connector sub-assembly comprising an optical ferrule; wherein the second portion of the glue body includes a pair of opposed snap hooks that are configured to engage a corresponding pair of opposed recesses of the connector sub-assembly; and wherein the optical fiber and the optical ferrule are optically coupled.
    • 坚固的光纤连接器组件包括基本上中空的插头壳体; 以及设置在所述基本上中空的插头壳体内的胶体; 其中所述胶体包括构造成接合并保持包括光纤和一个或多个强度构件的光缆的第一部分; 其中所述胶体包括第二部分,所述第二部分构造成接合并保持包括光学套圈的连接器子组件; 其中所述胶体的第二部分包括一对相对的卡钩,其构造成与所述连接器子组件的相应的一对相对的凹部接合; 并且其中所述光纤和所述光学套圈是光耦合的。