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31. 发明授权

US08202806B2 Method to avoid threshold voltage shift in thicker dielectric films 失效
标题翻译：避免较厚介质膜中阈值电压漂移的方法
公开(公告)号：US08202806B2
公开(公告)日：2012-06-19
申请号：US11242375
申请日：2005-10-03
申请人： Randhir P.S. Thakur , Ravi Iyer , Howard Rhodes
发明人： Randhir P.S. Thakur , Ravi Iyer , Howard Rhodes
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L23/3171 , H01L21/02129 , H01L21/02271 , H01L21/02304 , H01L21/02315 , H01L21/31612 , H01L21/3162 , H01L21/76828 , H01L21/76829 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.
摘要翻译：提供了一种制造具有降低的阈值电压偏移的集成电路的方法。在半导体衬底上形成非导电区域，在半导体衬底上形成有源区域。有源区由非导电区分开。势垒层和电介质层沉积在非导电区域上并在有源区上方。对集成电路施加热量，导致阻挡层退火。

32. 发明申请

US20110090920A1 PACKET COALESCING 有权
标题翻译：包装包装
公开(公告)号：US20110090920A1
公开(公告)日：2011-04-21
申请号：US12980682
申请日：2010-12-29
申请人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
发明人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC分类号： H04L12/66
CPC分类号： H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
摘要： In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
摘要翻译：一般来说，一方面，本公开内容描述了一种方法，其包括接收多个入口因特网协议分组，所述多个入口因特网协议分组中的每一个具有因特网协议报头和具有传输控制协议报头和传输控制的传输控制协议段协议有效载荷，其中属于相同传输控制协议/因特网协议的多个分组流。该方法还包括准备具有单个因特网协议报头的互联网协议分组和具有单个传输控制协议报头的单个传输控制协议段和由多个因特网协议分组的传输控制协议段有效载荷的组合形成的单个有效载荷。该方法还包括产生导致因特网协议分组的接收处理的信号。

33. 发明申请

US20100285238A1 METHODS OF FORMING GLASS ON A SUBSTRATE 失效
标题翻译：在基板上形成玻璃的方法
公开(公告)号：US20100285238A1
公开(公告)日：2010-11-11
申请号：US12843518
申请日：2010-07-26
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： C23C16/48
CPC分类号： C23C16/401
摘要： Disclosed is a deposition process for forming a glass film. An embodiment comprising the steps of disposing a substrate in a chemical vapor deposition chamber and exposing the substrate surface to a SiO2 precursor gas, a carrier gas, and optionally a dopant gas in the presence of ozone and exposing the reaction volume of the gases above the substrate surface to a high intensity light source.
摘要翻译：公开了一种用于形成玻璃膜的沉积工艺。一种实施方案，其包括以下步骤：在化学气相沉积室中设置衬底，并在臭氧存在下将衬底表面暴露于SiO 2前体气体，载体气体和任选的掺杂气体，并将气体的反应体积暴露于高于衬底表面到高强度光源。

34. 发明申请

US20090194818A1 Transistor Gate Forming Methods and Integrated Circuits 有权
标题翻译：晶体管栅极形成方法和集成电路
公开(公告)号：US20090194818A1
公开(公告)日：2009-08-06
申请号：US12424455
申请日：2009-04-15
申请人： D. V. Nirmal Ramaswamy , Ravi Iyer
发明人： D. V. Nirmal Ramaswamy , Ravi Iyer
IPC分类号： H01L27/092
CPC分类号： H01L21/28088 , H01L21/823842 , H01L29/78
摘要： A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.
摘要翻译：晶体管栅极形成方法包括形成第一和第二晶体管栅极。两个栅极中的每一个包括下金属层和上金属层。第一栅极的下金属层源自表现出与第二栅极的下金属层源自的沉积材料所表现出的功函数相同的功函数的沉积材料。然而，第一栅极的下部金属层表现出与第二栅极的下部金属层所表现的功函数不同的修正功函数。与第二栅极的下金属层相比，第一栅极的下金属层可以含有较少的氧和/或碳。与第二栅极的下金属层相比，第一栅极的下金属层可以含有更多的氮。第一栅极可以是n沟道栅极，第二栅极可以是p沟道栅极。

35. 发明授权

US07545009B2 Word lines for memory cells 有权
标题翻译：记忆单元的字线
公开(公告)号：US07545009B2
公开(公告)日：2009-06-09
申请号：US11072159
申请日：2005-03-04
申请人： Ravi Iyer , Yongjun Jeff Hu , Luan Tran , Brent Gilgen
发明人： Ravi Iyer , Yongjun Jeff Hu , Luan Tran , Brent Gilgen
IPC分类号： H01L29/78
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/76849 , H01L21/76855 , H01L21/7687 , H01L21/76889 , H01L23/485 , H01L27/10855 , H01L28/84 , H01L28/90 , H01L29/456 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.
摘要翻译：使用覆盖含硅材料的第一耐火金属材料和覆盖第一难熔金属材料的第二难熔金属材料来降低与含硅材料的接触电阻。每种难熔金属材料是含有难熔金属和杂质的导电材料。第一难熔金属材料是富含金属的材料，其含量低于化学计量水平的杂质。与第一难熔金属材料相比，第二难熔金属材料对杂质的亲和力较低。因此，第二难熔金属材料可以在退火或其它暴露于热的过程中用作杂质供体。这种杂质向第一难熔金属材料的净迁移限制了第一难熔金属材料和下面的含硅材料之间的金属硅化物界面的生长，从而提供与耐热性的欧姆接触。

36. 发明申请

US20070166920A1 Transistor gate forming methods and transistor structures 有权
标题翻译：晶体管栅极形成方法和晶体管结构
公开(公告)号：US20070166920A1
公开(公告)日：2007-07-19
申请号：US11716433
申请日：2007-03-08
申请人： Sanh Tang , Gordon Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh Tang , Gordon Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
摘要翻译：晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。填充层相对于金属层基本上可选择性地蚀刻。晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。本发明至少应用于三维晶体管结构。

37. 发明申请

US20070048941A1 Transistor gate forming methods and transistor structures 有权
公开(公告)号：US20070048941A1
公开(公告)日：2007-03-01
申请号：US11219077
申请日：2005-09-01
申请人： Sanh Tang , Gordon Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh Tang , Gordon Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.

38. 发明申请

US20060030162A1 Method to avoid threshold voltage shift in thicker dielectric films 失效
公开(公告)号：US20060030162A1
公开(公告)日：2006-02-09
申请号：US11242375
申请日：2005-10-03
申请人： Randhir Thakur , Ravi Iyer , Howard Rhodes
发明人： Randhir Thakur , Ravi Iyer , Howard Rhodes
IPC分类号： H01L21/469
CPC分类号： H01L23/3171 , H01L21/02129 , H01L21/02271 , H01L21/02304 , H01L21/02315 , H01L21/31612 , H01L21/3162 , H01L21/76828 , H01L21/76829 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.

39. 发明申请

US20050161721A1 Word lines for memory cells 有权
标题翻译：记忆单元的字线
公开(公告)号：US20050161721A1
公开(公告)日：2005-07-28
申请号：US11072159
申请日：2005-03-04
申请人： Ravi Iyer , Yongjun Hu , Luan Tran , Brent Gilgen
发明人： Ravi Iyer , Yongjun Hu , Luan Tran , Brent Gilgen
IPC分类号： H01L21/02 , H01L21/285 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L29/45 , H01L27/108
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/76849 , H01L21/76855 , H01L21/7687 , H01L21/76889 , H01L23/485 , H01L27/10855 , H01L28/84 , H01L28/90 , H01L29/456 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.
摘要翻译：使用覆盖含硅材料的第一耐火金属材料和覆盖第一难熔金属材料的第二难熔金属材料来降低与含硅材料的接触电阻。每种难熔金属材料是含有难熔金属和杂质的导电材料。第一难熔金属材料是富含金属的材料，其含量低于化学计量水平的杂质。与第一难熔金属材料相比，第二难熔金属材料对杂质的亲和力较低。因此，第二难熔金属材料可以在退火或其它暴露于热的过程中用作杂质供体。这种杂质向第一难熔金属材料的净迁移限制了第一难熔金属材料和下面的含硅材料之间的金属硅化物界面的生长，从而提供与耐热性的欧姆接触。

40. 发明授权

US06864561B2 Method and apparatus for reducing fixed charge in semiconductor device layers 失效
标题翻译：用于减少半导体器件层中的固定电荷的方法和装置
公开(公告)号：US06864561B2
公开(公告)日：2005-03-08
申请号：US10727889
申请日：2003-12-04
申请人： Ravi Iyer , Randhir P. S. Thakur , Howard E. Rhodes
发明人： Ravi Iyer , Randhir P. S. Thakur , Howard E. Rhodes
IPC分类号： H01L21/316 , H01L23/58 , H01L21/31
CPC分类号： H01L21/02164 , H01L21/02129 , H01L21/02271 , H01L21/31612 , H01L21/31625
摘要： The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices.
摘要翻译：通过使诸如TEOS的有机前体与O 3反应，沉积在半导体器件上的硼磷硅玻璃绝缘膜中的固定电荷被还原。当在高于约480摄氏度的温度下完成时，所得膜中的碳水平似乎降低，导致场晶体管器件的阈值电压更高。

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