专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US5935336A Apparatus to increase gas residence time in a reactor 失效
公开(公告)号：US5935336A
公开(公告)日：1999-08-10
申请号：US950549
申请日：1997-10-15
申请人： Gurtej S. Sandhu , Ravi Iyer , Sujit Sharan
发明人： Gurtej S. Sandhu , Ravi Iyer , Sujit Sharan
IPC分类号： C23C16/44 , C23C16/455 , C23C16/509 , C23C16/00
CPC分类号： C23C16/45517 , C23C16/4412 , C23C16/455 , C23C16/45591 , C23C16/509
摘要： An apparatus is provided for controlling the flow of gaseous reactants in a CVD reactor through the use of a body having interior and exterior regions, in which the body defines at least one flow path between the interior and exterior regions so as to create a pressure drop from the interior to the exterior of the body within the chamber. The body is disposed in a reaction chamber with a first area proximate a gaseous reactant inlet and a second area proximate a substrate support such that the substrate is positioned in proximity to the interior of the body. As such, gaseous reactants introduced into the interior of said chamber through the inlet create a pressure drop between the interior and the exterior of the body. In a preferred embodiment, the body is cylindrically shaped and contains perforations providing the flow paths. Preferably, the perforations are either more numerous or larger in the second area than the first area to create a pressure gradient in the interior of the body. Alternatively, the perforations may be uniform in size and uniformly distributed over the body or the perforations can be configured to create a desired pressure differential in the body to support a plasma created in the body and control its location.

62. 发明授权

US5910684A Integrated circuitry 失效
标题翻译：集成电路
公开(公告)号：US5910684A
公开(公告)日：1999-06-08
申请号：US708116
申请日：1996-09-03
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： H01L21/768 , H01L23/522 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/768 , H01L21/76838 , H01L23/5222 , H01L2924/0002
摘要： A semiconductor processing method of forming an electrically conductive interconnect line having an electrical conductive covering predominately coextensive therewith, includes, a) providing an conductive interconnect line over a first electrically insulating material, the line having a top and sidewalls; b) selectively depositing a second electrically insulating material layer over the interconnect line and the first insulating material in a manner which deposits a greater thickness of the second insulating material atop the interconnect line than a thickness of the second insulating material over the first insulating material; c) anisotropically etching the second insulating material layer inwardly to at least the first insulating material yet leaving second insulating material over the top and the sidewalls of the interconnect line; and d) providing an electrically conductive layer over the anisotropically etched second insulating layer to form a conductive layer which is predominately coextensive with the interconnect line over the etched second insulating material. The method further comprises provision of a base electrically conductive layer beneath the first insulating material, with the anisotropically etching step etching through the first insulating material to the base conductive layer, and the conductive layer being provided in electrical connection with the base conductive layer. Integrated circuitry produced by the method and other methods is also disclosed.
摘要翻译：一种形成具有与其主要共同延伸的导电覆盖层的导电互连线的半导体处理方法包括：a）在第一电绝缘材料上提供导电互连线，该线具有顶部和侧壁; b）在所述互连线和所述第一绝缘材料上选择性地沉积第二电绝缘材料层，所述第二电绝缘材料层以在所述互连线上方沉积更大厚度的所述第二绝缘材料的厚度大于所述第一绝缘材料上所述第二绝缘材料的厚度; c）将第二绝缘材料层向内各向异性地蚀刻至少至少第一绝缘材料，同时将第二绝缘材料留在互连线的顶部和侧壁上; 以及d）在各向异性蚀刻的第二绝缘层上方设置导电层，以形成导电层，该导电层主要与蚀刻的第二绝缘材料上的互连线共同延伸。该方法还包括在第一绝缘材料下面提供基底导电层，各向异性蚀刻步骤通过第一绝缘材料蚀刻到基底导电层，并且导电层设置成与基底导电层电连接。还公开了通过该方法和其它方法生产的集成电路。

63. 发明授权

US5856236A Method of depositing a smooth conformal aluminum film on a refractory metal nitride layer 失效
$Method of depositing a smooth conformal aluminum film on a refractory metal nitride layer$
标题翻译：在难熔金属氮化物层上沉积光滑的保形铝膜的方法
公开(公告)号：US5856236A
公开(公告)日：1999-01-05
申请号：US663996
申请日：1996-06-14
申请人： Gilbert Lai , Gurtej S. Sandhu , Ravi Iyer , Brian A. Vaartstra
发明人： Gilbert Lai , Gurtej S. Sandhu , Ravi Iyer , Brian A. Vaartstra
IPC分类号： C23C16/02 , C23C16/44 , H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/28568 , C23C16/0272 , C23C16/44 , H01L21/28518 , H01L21/28556 , H01L21/28562 , H01L21/76877
摘要： A method of forming a conformal aluminum film on a refractory metal nitride layer is provided and includes positioning a substrate having the refractory metal nitride layer thereon within a chemical vapor deposition chamber; establishing a nominal temperature for the substrate; introducing a carrier gas containing a gaseous, metalorganic precursor into the chamber for a time sufficient to form a metallic seed layer; and introducing a carrier gas containing a gaseous aluminum metalorganic precursor into the chamber for a time sufficient to form a conformal aluminum metal film over the metal refractory nitride layer.
摘要翻译：提供了在难熔金属氮化物层上形成共形铝膜的方法，包括将其上具有难熔金属氮化物层的基板定位在化学气相沉积室内; 建立基板的标称温度; 将含有气态金属有机前体的载气引入室中足以形成金属种子层的时间; 并将含有气态铝金属有机前体的载气引入室中足以在金属耐火氮化物层上形成共形铝金属膜的时间。

64. 发明授权

US5382550A Method of depositing SiO.sub.2 on a semiconductor substrate 失效
标题翻译：在半导体衬底上沉积SiO 2的方法
公开(公告)号：US5382550A
公开(公告)日：1995-01-17
申请号：US103392
申请日：1993-08-05
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： H01L21/316 , H01L21/02
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/31612 , H01L21/31633 , Y10S148/118
摘要： A deposition method of reducing fixed charge in a layer of silicon dioxide includes: a) providing a gaseous organosilicon compound to a chemical vapor deposition reactor having a semiconductor wafer positioned therein; b) providing an oxidizing gas to the reactor for reaction with the organosilicon compound; c) feeding a gaseous hydrogen containing source to the reactor; and d) reacting the organosilicon compound, oxidizing gas and gaseous hydrogen containing source to deposit a layer of silicon dioxide on the wafer, the hydrogen containing source gas effectively reacting with the organosilicon compound to produce reduced fixed charge in the deposited silicon dioxide layer over that which would be present if no hydrogen containing source gas were fed to the reactor under otherwise identical reacting conditions. Another method of depositing a layer of silicon dioxide on a semiconductor wafer comprises: a) providing a gaseous organosilicon compound to a chemical vapor deposition reactor having a semiconductor wafer positioned therein; and b) providing an oxidizing gas to the reactor, and reacting the oxidizing gas with the gaseous organosilicon compound in the reactor to deposit a layer of silicon dioxide on the wafer, the oxidizing gas comprising a compound having an N--O bond.
摘要翻译：减少二氧化硅层中的固定电荷的沉积方法包括：a）向其中定位有半导体晶片的化学气相沉积反应器提供气态有机硅化合物; b）向反应器提供氧化气体以与有机硅化合物反应; c）将含气态的氢气源送入反应器; 和d）使有机硅化合物，氧化气体和含氢气气体源反应以在晶片上沉积二氧化硅层，含氢源气体与有机硅化合物有效反应以在沉积的二氧化硅层中产生减少的固定电荷，超过该沉积二氧化硅层如果在其他相同的反应条件下不将含氢的源气体进料到反应器中，则其将存在。在半导体晶片上沉积二氧化硅层的另一种方法包括：a）向其中定位有半导体晶片的化学气相沉积反应器提供气态有机硅化合物; 和b）向所述反应器提供氧化气体，并且使所述氧化气体与所述反应器中的所述气态有机硅化合物反应以在所述晶片上沉积二氧化硅层，所述氧化气体包含具有N-O键的化合物。

65. 发明授权

US09395994B2 Embedded branch prediction unit 有权
标题翻译：嵌入式分支预测单元
公开(公告)号：US09395994B2
公开(公告)日：2016-07-19
申请号：US13992723
申请日：2011-12-30
申请人： Xiaowei Jiang , Srihari Makineni , Zhen Fang , Dmitri Pavlov , Ravi Iyer
发明人： Xiaowei Jiang , Srihari Makineni , Zhen Fang , Dmitri Pavlov , Ravi Iyer
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/30058
摘要： In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.
摘要翻译：根据本发明的一些实施例，用于嵌入式控制器的分支预测单元可以与指令提取单元相关联而不是解码级放置。另外，分支预测单元也可以不包括分支预测器。此外，返回地址堆栈可以与指令解码级相关联，并且在结构上与分支预测单元分离。在某些情况下，这种布置减少了分支预测单元的面积以及功耗。

66. 发明申请

US20130345152A1 COMPOSITIONS COMPRISING RECOMBINANT COWPOX VIRUS PROTEIN CPXV014 审中-公开
标题翻译：包含重组COWPOX病毒蛋白CPXV014的组合物
公开(公告)号：US20130345152A1
公开(公告)日：2013-12-26
申请号：US13922850
申请日：2013-06-20
申请人： Klaus Frueh , David M. Edwards , Ravi Iyer , Dina Alzhanova
发明人： Klaus Frueh , David M. Edwards , Ravi Iyer , Dina Alzhanova
IPC分类号： C07K14/005
CPC分类号： C07K14/005 , C12N2710/24122 , C12N2710/24133
摘要： Disclosed herein are expression vectors that encode cowpox virus protein CPXV014 and homologs thereof that are useful in inhibiting CD3/CD28 mediated T cell stimulation. Further disclosed are polypeptide compositions comprising CPXV014 and homologs thereof as well as methods of inhibiting CD3/CD28 mediated T cell stimulation using the polypeptide compositions.
摘要翻译：本文公开了编码牛痘病毒蛋白质CPXV014的表达载体及其同源物，其可用于抑制CD3 / CD28介导的T细胞刺激。还公开了包含CPXV014及其同系物的多肽组合物，以及使用多肽组合物抑制CD3 / CD28介导的T细胞刺激的方法。

67. 发明授权

US08420170B2 Methods of forming glass on a substrate 失效
标题翻译：在基材上形成玻璃的方法
公开(公告)号：US08420170B2
公开(公告)日：2013-04-16
申请号：US12843518
申请日：2010-07-26
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： C23C16/00
CPC分类号： C23C16/401
摘要： Disclosed is a deposition process for forming a glass film. An embodiment comprising the steps of disposing a substrate in a chemical vapor deposition chamber and exposing the substrate surface to a SiO2 precursor gas, a carrier gas, and optionally a dopant gas in the presence of ozone and exposing the reaction volume of the gases above the substrate surface to a high intensity light source.
摘要翻译：公开了一种用于形成玻璃膜的沉积工艺。一种实施方案，其包括以下步骤：在化学气相沉积室中设置衬底，并在臭氧存在下将衬底表面暴露于SiO 2前体气体，载体气体和任选的掺杂气体，并将气体的反应体积暴露于高于衬底表面到高强度光源。

68. 发明授权

US08349687B2 Transistor gate forming methods and transistor structures 有权
标题翻译：晶体管栅极形成方法和晶体管结构
公开(公告)号：US08349687B2
公开(公告)日：2013-01-08
申请号：US12977969
申请日：2010-12-23
申请人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L29/76
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
摘要翻译：晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。填充层相对于金属层基本上可选择性地蚀刻。晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。本发明至少应用于三维晶体管结构。

69. 发明授权

US08089128B2 Transistor gate forming methods and integrated circuits 有权
标题翻译：晶体管栅极形成方法和集成电路
公开(公告)号：US08089128B2
公开(公告)日：2012-01-03
申请号：US12424455
申请日：2009-04-15
申请人： D. V. Nirmal Ramaswamy , Ravi Iyer
发明人： D. V. Nirmal Ramaswamy , Ravi Iyer
IPC分类号： H01L27/092
CPC分类号： H01L21/28088 , H01L21/823842 , H01L29/78
摘要： A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.
摘要翻译：晶体管栅极形成方法包括形成第一和第二晶体管栅极。两个栅极中的每一个包括下金属层和上金属层。第一栅极的下金属层源自表现出与第二栅极的下金属层源自的沉积材料所表现的功函数相同的功函数的沉积材料。然而，第一栅极的下部金属层表现出与第二栅极的下部金属层所表现的功函数不同的修正功函数。与第二栅极的下金属层相比，第一栅极的下金属层可以含有较少的氧和/或碳。与第二栅极的下金属层相比，第一栅极的下金属层可以含有更多的氮。第一栅极可以是n沟道栅极，第二栅极可以是p沟道栅极。

70. 发明授权

US07977236B2 Method of forming a transistor gate of a recessed access device, method of forming a recessed transistor gate and a non-recessed transistor gate, and method of fabricating an integrated circuit 有权
标题翻译：形成凹陷式存取器件的晶体管栅极的方法，形成凹陷晶体管栅极和非凹槽晶体管栅极的方法以及制造集成电路的方法
公开(公告)号：US07977236B2
公开(公告)日：2011-07-12
申请号：US12476364
申请日：2009-06-02
申请人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
IPC分类号： H01L21/4763
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.
摘要翻译：为嵌入硅完全硅化提供了方法和结构。在沟槽内提供硅。在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。示例性的混合物包括80％的镍和20％的钴。尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式