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81. 发明申请

US20050121794A1 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US20050121794A1
公开(公告)日：2005-06-09
申请号：US11026822
申请日：2004-12-29
申请人： Werner Juengling , Kirk Prall , Ravi Iyer , Gurtej Sandhu , Guy Blalock
发明人： Werner Juengling , Kirk Prall , Ravi Iyer , Gurtej Sandhu , Guy Blalock
IPC分类号： H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L29/40
CPC分类号： H01L23/5222 , H01L21/02115 , H01L21/02118 , H01L21/02203 , H01L21/02274 , H01L21/02282 , H01L21/02337 , H01L21/02362 , H01L21/31695 , H01L21/7682 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.
摘要翻译：本发明包括在导电元件之间形成绝缘材料的方法。在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

82. 发明授权

US06841463B1 Interlevel dielectric structure and method of forming same 失效
标题翻译：电介质结构及其形成方法
公开(公告)号：US06841463B1
公开(公告)日：2005-01-11
申请号：US09627381
申请日：2000-07-28
申请人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
发明人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76837
摘要： An interlevel dielectric structure includes first and second dielectric layers between which are located lines of a conductive material with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.
摘要翻译：层间电介质结构包括第一和第二电介质层，它们之间位于导电材料的导线之间，其中电介质材料位于导电材料线之间的空间中，电介质材料的下表面延伸低于导电线路的下表面材料相邻，并且电介质材料的上表面比邻近导电材料的上表面延伸得更高，从而减少导电材料线之间的条纹和总电容。具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工。公开了形成层间电介质结构的各种方法。

83. 发明授权

US06784122B2 Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers 失效
公开(公告)号：US06784122B2
公开(公告)日：2004-08-31
申请号：US10371674
申请日：2003-02-21
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： C23C1640
CPC分类号： H01L21/02164 , C03C17/02 , C23C16/0245 , C23C16/0272 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/31612 , H01L21/76826 , H01L21/76834 , H01L21/76837
摘要： A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 comprises placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.

84. 发明授权

US06777346B2 Planarization using plasma oxidized amorphous silicon 失效
标题翻译：使用等离子体氧化非晶硅的平面化
公开(公告)号：US06777346B2
公开(公告)日：2004-08-17
申请号：US09059865
申请日：1998-04-14
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： H01L2131
CPC分类号： H01L21/02238 , H01L21/02252 , H01L21/3105 , H01L21/31051 , H01L21/316 , H01L21/31662 , H01L21/32105
摘要： A planarization process for filling spaces between patterned metal features formed over a surface of a semiconductor substrate. The patterned metal features are preferably coated with a dielectric barrier. The dielectric barrier is coated with an material that expands during oxidation or nitridization to a thickness about half the depth of the space between metallized features. The layer is then plasma oxidized using an RF or ECR plasma at low temperature with an oxygen ambient. Alternatively, the layer is plasma nitridized at low temperature. The plasma oxidation or nitridization is continued until the expandable material is converted to a dielectric and has expanded to fill the space between patterned metal features. Optionally, the process can be followed by a mechanical or chemical mechanical planarization step.
摘要翻译：用于填充在半导体衬底的表面上形成的图案化金属特征之间的空间的平坦化处理。图案化的金属特征优选地涂覆有电介质阻挡层。电介质阻挡层涂覆有在氧化或氮化期间膨胀至金属化特征之间的空间深度的大约一半厚度的材料。然后使用RF或ECR等离子体在低温和氧气氛下对该层进行等离子体氧化。或者，该层在低温下被等离子体氮化。等离子体氧化或氮化继续直到可膨胀材料转化为电介质并且已经膨胀以填充图案化的金属特征之间的空间。任选地，该过程可以之后是机械或化学机械平面化步骤。

85. 发明授权

US06727190B2 Method of forming fluorine doped boron-phosphorous silicate glass (F-BPSG) insulating materials 失效
标题翻译：氟掺杂硼硅酸盐玻璃（F-BPSG）绝缘材料的形成方法
公开(公告)号：US06727190B2
公开(公告)日：2004-04-27
申请号：US09146839
申请日：1998-09-03
申请人： Anand Srinivasan , Gurtej Sandhu , Ravi Iyer
发明人： Anand Srinivasan , Gurtej Sandhu , Ravi Iyer
IPC分类号： H01L21316
CPC分类号： H01L21/02131 , C23C16/401 , H01L21/02271 , H01L21/31629
摘要： In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants. In yet another aspect, the invention includes a method of forming a phosphorus-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising triethoxy fluorosilane, a phosphorus-containing precursor, and ozone within the reaction chamber; and c) depositing a phosphorus-doped silicon oxide having Si—F bonds onto the substrate from the reactants.
摘要翻译：一方面，本发明包括一种形成绝缘材料的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含Si，F和臭氧的反应物; 以及c）从所述反应物沉积包含氟，硅和氧的绝缘材料到所述衬底上。另一方面，本发明包括形成具有Si-F键的掺硼氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含硼前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的掺硼氧化硅到所述衬底上。另一方面，本发明包括形成具有Si-F键的磷掺杂氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含磷前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的磷掺杂的氧化硅到所述衬底上。

86. 发明授权

US06677241B1 Methods of forming a gate stack that is void of silicon clusters within a metallic silicide film thereof 有权
公开(公告)号：US06677241B1
公开(公告)日：2004-01-13
申请号：US09614113
申请日：2000-07-12
申请人： Pai-Hung Pan , Louie Liu , Ravi Iyer
发明人： Pai-Hung Pan , Louie Liu , Ravi Iyer
IPC分类号： H01L21302
摘要： A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

87. 发明授权

US06613673B2 Technique for elimination of pitting on silicon substrate during gate stack etch 有权
公开(公告)号：US06613673B2
公开(公告)日：2003-09-02
申请号：US09942191
申请日：2001-08-29
申请人： Pai-Hung Pan , Louie Liu , Ravi Iyer
发明人： Pai-Hung Pan , Louie Liu , Ravi Iyer
IPC分类号： H01L2100
CPC分类号： H01L21/28052
摘要： A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

88. 发明授权

US06551665B1 Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers 失效
公开(公告)号：US06551665B1
公开(公告)日：2003-04-22
申请号：US08841908
申请日：1997-04-17
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： C23C1640
CPC分类号： H01L21/02164 , C03C17/02 , C23C16/0245 , C23C16/0272 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/31612 , H01L21/76826 , H01L21/76834 , H01L21/76837
摘要： A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 is disclosed. The entire method, which can be performed in a single cluster tool and even in a single chamber, begins by placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber. A “clean” silicate glass base layer that is substantially free of carbon particle impurities on an upper surface is then formed on the wafer surface in one of two ways. The first employs plasma-enhanced chemical vapor deposition using TEOS and diatomic oxygen gases as precursors to first deposit a “dirty” silicate glass base layer having carbon particle impurities imbedded on an upper surface. The dirty base layer is then transformed to a clean base layer by subjecting it to a plasma treatment, which involves flowing a mixture of a diamagnetic oxygen-containing oxidant, such as ozone or hydrogen peroxide, and diatomic oxygen gas into the chamber and striking an RF plasma at a power density setting of about 0.25 to 3.0 watts/cm2 for a period of from 30-300 seconds. It is hypothesized that the plasma treatment burns off the impurities, which are present in the PECVD-deposited base layer and which may be responsible for certain hydrophilic surface effects which repel TEOS molecules. The plasma treatment also creates a high degree of surface uniformity on the PECVD-deposited glass layer. The second way of forming a clean silicate glass base layer involves flowing hydrogen peroxide vapor and at least one gaseous compound selected from the group consisting of silane and disilane into the deposition chamber. Following the formation of the clean base layer, a subsequent glass layer is deposited over the PECVD-deposited glass layer in the same chamber or cluster tool using chemical vapor deposition and TEOS and ozone as precursor compounds.

89. 发明授权

US06501179B2 Constructions comprising insulative materials 有权
标题翻译：建筑物包括绝缘材料
公开(公告)号：US06501179B2
公开(公告)日：2002-12-31
申请号：US09921861
申请日：2001-08-02
申请人： Werner Juengling , Kirk D. Prall , Ravi Iyer , Gurtej S. Sandhu , Guy Blalock
发明人： Werner Juengling , Kirk D. Prall , Ravi Iyer , Gurtej S. Sandhu , Guy Blalock
IPC分类号： H01L23485
CPC分类号： H01L21/7682 , H01L21/02115 , H01L21/02118 , H01L21/02167 , H01L21/02203 , H01L21/02274 , H01L21/02282 , H01L21/02362 , H01L21/31695 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L23/5222 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , Y10T428/12014 , Y10T428/24149 , Y10T428/249921 , Y10T428/25 , Y10T428/259 , H01L2924/00
摘要： The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.
摘要翻译：本发明包括在导电元件之间形成绝缘材料的方法。在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

90. 发明授权

US06498109B2 System and method for plasma etching 失效
标题翻译：等离子体蚀刻的系统和方法
公开(公告)号：US06498109B2
公开(公告)日：2002-12-24
申请号：US09796914
申请日：2001-03-01
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： H01L2100
CPC分类号： H01L21/67069 , H01L21/32136
摘要： A process for plasma etching metal films comprising the steps of forming a noble gas plasma, then transporting the noble gas plasma to a mixing chamber. An organohalide is added to the noble gas plasma in the mixing chamber. The organohalide is selected to have a vapor pressure allowing the formation of activated complexes to etch the metal films and form organometallic compounds as the etch byproducts. The activated complexes thus formed are transported downstream to an etching chamber. In the etching chamber the selected substrate is exposed to the activated complexes, causing the substrate to be etched and organometallic compounds to be formed as byproducts from the reaction of the activated complexes and etching of the substrate. The organometallic byproducts can then be removed from the etch chamber.
摘要翻译：一种用于等离子体蚀刻金属膜的方法，包括以下步骤：形成惰性气体等离子体，然后将稀有气体等离子体输送到混合室。在混合室中的惰性气体等离子体中加入有机卤化物。选择有机卤化物具有允许形成活化复合物的蒸汽压力以蚀刻金属膜并形成有机金属化合物作为蚀刻副产物。如此形成的活化的复合体在下游被传送到蚀刻室。在蚀刻室中，所选择的基底暴露于活化的复合物，导致基底被蚀刻，并且有机金属化合物由于活化复合物的反应和基底的蚀刻而被形成为副产物。然后可以从蚀刻室中除去有机金属副产物。

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