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1. 发明授权

US08022772B2 Cascode amplifier with protection circuitry 有权
标题翻译：带保护电路的串联放大器
公开(公告)号：US08022772B2
公开(公告)日：2011-09-20
申请号：US12407729
申请日：2009-03-19
申请人： Marco Cassia , Gurkanwal Singh Sahota
发明人： Marco Cassia , Gurkanwal Singh Sahota
IPC分类号： H03F1/22
CPC分类号： H03F1/223 , H03F1/523 , H03F3/211 , H03F3/72 , H03F2200/27 , H03F2200/294 , H03F2203/7206 , H03F2203/7215 , H03F2203/7236 , H03G1/0088
摘要： A cascode amplifier with protection circuitry is described. In one exemplary design, the amplifier includes multiple branches coupled in parallel, with at least one branch being switchable between “on” and “off” states. Each switchable branch includes a gain transistor coupled to a cascode transistor. The gain transistor amplifies an input signal and provides an amplified signal in the on state and does not amplify the input signal in the off state. The cascode transistor buffers the amplified signal and provides an output signal in the on state. The output signal swing may be split between the gain transistor and the cascode transistor in both the on and off states with the protection circuitry. Each transistor may then observe a fraction of the voltage swing. The voltage splitting in the off state may be achieved by floating the gain transistor and shorting the gate and source of the cascode transistor.
摘要翻译：描述了具有保护电路的共源共栅放大器。在一个示例性设计中，放大器包括并联耦合的多个分支，至少一个分支可在“开”和“关”状态之间切换。每个可切换分支包括耦合到共源共栅晶体管的增益晶体管。增益晶体管放大输入信号，并将放大的信号提供为导通状态，并且不将输入信号放大在关闭状态。共源共栅晶体管缓冲放大的信号，并提供处于导通状态的输出信号。在保护电路中，输出信号摆幅可以在开关状态和断开状态之间在增益晶体管和共源共栅晶体管之间分开。然后，每个晶体管可以观察电压摆幅的一小部分。断开状态下的分压可以通过使增益晶体管浮置并使共源共栅晶体管的栅极和源极短路来实现。

2. 发明申请

US20100291888A1 MULTI-MODE MULTI-BAND POWER AMPLIFIER MODULE 有权
标题翻译：多模多功率放大器模块
公开(公告)号：US20100291888A1
公开(公告)日：2010-11-18
申请号：US12575414
申请日：2009-10-07
申请人： Aristotele Hadjichristos , Puay Hoe See , Babak Nejati , Guy Klemens , Norman Frederick, JR. , Gurkanwal Singh Sahota , Marco Cassia , Nathan Pletcher , Yu Zhao , Thomas Myers
发明人： Aristotele Hadjichristos , Puay Hoe See , Babak Nejati , Guy Klemens , Norman Frederick, JR. , Gurkanwal Singh Sahota , Marco Cassia , Nathan Pletcher , Yu Zhao , Thomas Myers
IPC分类号： H04B1/04
CPC分类号： H04B1/0458 , H03F1/0277 , H03F3/24 , H03F3/72 , H03F2203/7236 , H04B1/0483
摘要： A multi-mode multi-band power amplifier (PA) module is described. In an exemplary design, the PA module includes multiple power amplifiers, multiple matching circuits, and a set of switches. Each power amplifier provides power amplification for its input signal when selected. Each matching circuit provides impedance matching and filtering for its power amplifier and provides a respective output signal. The switches configure the power amplifiers to support multiple modes, with each mode being for a particular radio technology. Each power amplifier supports at least two modes. The PA module may further include a driver amplifier and an additional matching circuit. The driver amplifier amplifies an input signal and provides an amplified signal to the power amplifiers. The additional matching circuit combines the outputs of other matching circuits and provides an output signal with higher output power. The driver amplifier and the power amplifiers can support multiple output power levels.
摘要翻译：描述了多模式多频带功率放大器（PA）模块。在示例性设计中，PA模块包括多个功率放大器，多个匹配电路和一组开关。每个功率放大器在选择时为其输入信号提供功率放大。每个匹配电路为其功率放大器提供阻抗匹配和滤波，并提供相应的输出信号。这些开关配置功率放大器以支持多种模式，每种模式都适用于特定的无线电技术。每个功率放大器至少支持两种模式。 PA模块还可以包括驱动器放大器和附加匹配电路。驱动器放大器放大输入信号并向功率放大器提供放大的信号。附加匹配电路组合其他匹配电路的输出，并提供具有较高输出功率的输出信号。驱动器放大器和功率放大器可以支持多个输出功率电平。

3. 发明申请

US20100237945A1 CASCODE AMPLIFIER WITH PROTECTION CIRCUITRY 有权
标题翻译：带保护电路的CASCODE放大器
公开(公告)号：US20100237945A1
公开(公告)日：2010-09-23
申请号：US12407729
申请日：2009-03-19
申请人： Marco Cassia , Gurkanwal Singh Sahota
发明人： Marco Cassia , Gurkanwal Singh Sahota
IPC分类号： H03F3/16
CPC分类号： H03F1/223 , H03F1/523 , H03F3/211 , H03F3/72 , H03F2200/27 , H03F2200/294 , H03F2203/7206 , H03F2203/7215 , H03F2203/7236 , H03G1/0088
摘要： A cascode amplifier with protection circuitry is described. In one exemplary design, the amplifier includes multiple branches coupled in parallel, with at least one branch being switchable between “on” and “off” states. Each switchable branch includes a gain transistor coupled to a cascode transistor. The gain transistor amplifies an input signal and provides an amplified signal in the on state and does not amplify the input signal in the off state. The cascode transistor buffers the amplified signal and provides an output signal in the on state. The output signal swing may be split between the gain transistor and the cascode transistor in both the on and off states with the protection circuitry. Each transistor may then observe a fraction of the voltage swing. The voltage splitting in the off state may be achieved by floating the gain transistor and shorting the gate and source of the cascode transistor.
摘要翻译：描述了具有保护电路的共源共栅放大器。在一个示例性设计中，放大器包括并联耦合的多个分支，至少一个分支可在“开”和“关”状态之间切换。每个可切换分支包括耦合到共源共栅晶体管的增益晶体管。增益晶体管放大输入信号，并将放大的信号提供为导通状态，并且不将输入信号放大在关闭状态。共源共栅晶体管缓冲放大的信号，并提供处于导通状态的输出信号。在保护电路中，输出信号摆幅可以在开关状态和断开状态之间在增益晶体管和共源共栅晶体管之间分开。然后，每个晶体管可以观察电压摆幅的一小部分。断开状态下的分压可以通过使增益晶体管浮置并使共源共栅晶体管的栅极和源极短路来实现。

4. 发明授权

US08964821B2 Shared feedback for adaptive transmitter pre-distortion 有权
标题翻译：自适应发射机预失真的共享反馈
公开(公告)号：US08964821B2
公开(公告)日：2015-02-24
申请号：US13364065
申请日：2012-02-01
申请人： Philip D. Coan , Paul J. Draxler , Roberto Rimini , Thomas D. Marra , Gurkanwal Singh Sahota , Steven C. Ciccarelli , Shrenik Patel
发明人： Philip D. Coan , Paul J. Draxler , Roberto Rimini , Thomas D. Marra , Gurkanwal Singh Sahota , Steven C. Ciccarelli , Shrenik Patel
IPC分类号： H04B1/38 , H04L5/16 , H04L27/36 , H03F1/32 , H03F3/195 , H03F3/24 , H03F3/68 , H03F3/72 , H04B7/08
CPC分类号： H04L27/368 , H03F1/3247 , H03F3/195 , H03F3/245 , H03F3/68 , H03F3/72 , H03F2201/3212 , H03F2203/7221 , H03F2203/7236 , H04B7/0825
摘要： A modem is described. The modem includes a transmitter. The transmitter includes a digital pre-distortion module and a power amplifier. The modem also includes one or more selected shared receivers. The one or more selected shared receivers generate a feedback signal for the digital pre-distortion module. The modem further includes a feedback switch. The feedback switch selectively couples the one or more selected shared receivers to an output of the transmitter.
摘要翻译：调制解调器被描述。调制解调器包括发射机。发射机包括数字预失真模块和功率放大器。调制解调器还包括一个或多个选择的共享接收器。一个或多个选择的共享接收器产生用于数字预失真模块的反馈信号。调制解调器还包括反馈开关。反馈开关将一个或多个选择的共享接收机选择性地耦合到发射机的输出。

5. 发明授权

US08665028B2 Amplifier with integrated filter 有权
标题翻译：带集成滤波器的放大器
公开(公告)号：US08665028B2
公开(公告)日：2014-03-04
申请号：US13543532
申请日：2012-07-06
申请人： Tae Wook Kim , Guy Klemens , Kenneth Charles Barnett , Susanta Sengupta , Gurkanwal Singh Sahota
发明人： Tae Wook Kim , Guy Klemens , Kenneth Charles Barnett , Susanta Sengupta , Gurkanwal Singh Sahota
IPC分类号： H03F3/04
CPC分类号： H03F1/223 , H03F3/195 , H03F3/45188 , H03F3/45475 , H03F3/72 , H03F2200/168 , H03F2200/294 , H03F2200/451 , H03F2203/45034 , H03F2203/45058 , H03F2203/45138 , H03F2203/45296 , H03F2203/45301 , H03F2203/45316 , H03F2203/45396 , H03F2203/7239 , H03G1/0017 , H03G1/0029 , H03G1/0088 , H03G3/3052 , H03G3/3078
摘要： An amplifier with integrated filter (e.g., an LNA) is described. In one design, the amplifier may include a gain stage, a filter stage, and a buffer stage. The gain stage may provide signal amplification for an input signal. The filter stage may provide filtering for the input signal. The buffer stage may buffer a filtered signal from the filter stage. The amplifier may further include a second filter stage and a second buffer stage. The second filter stage may provide additional filtering for the input signal. The second buffer stage may buffer a second filtered signal from the second filter stage. All of the stages may be stacked and coupled between a supply voltage and circuit ground. The filter stage(s) may implement an elliptical lowpass filter. Each filter stage may include an inductor and a capacitor coupled in parallel and forming a resonator tank to attenuate interfering signals.
摘要翻译：描述了具有集成滤波器（例如，LNA）的放大器。在一种设计中，放大器可以包括增益级，滤波级和缓冲级。增益级可以为输入信号提供信号放大。滤波器级可以为输入信号提供滤波。缓冲级可以缓冲来自滤波级的滤波信号。放大器还可以包括第二滤波器级和第二缓冲级。第二滤波器级可以为输入信号提供额外的滤波。第二缓冲级可以缓冲来自第二滤波级的第二滤波信号。所有级可以堆叠并耦合在电源电压和电路接地之间。滤波器级可以实现椭圆形低通滤波器。每个滤波器级可以包括并联耦合的电感器和电容器，并形成谐振器箱以衰减干扰信号。

6. 发明申请

US20120274403A1 AMPLIFIER WITH INTEGRATED FILTER 有权
标题翻译：具有集成滤波器的放大器
公开(公告)号：US20120274403A1
公开(公告)日：2012-11-01
申请号：US13543532
申请日：2012-07-06
申请人： Tae Wook Kim , Guy Klemens , Kenneth Charles Barnett , Susanta Sengupta , Gurkanwal Singh Sahota
发明人： Tae Wook Kim , Guy Klemens , Kenneth Charles Barnett , Susanta Sengupta , Gurkanwal Singh Sahota
IPC分类号： H03G3/30
CPC分类号： H03F1/223 , H03F3/195 , H03F3/45188 , H03F3/45475 , H03F3/72 , H03F2200/168 , H03F2200/294 , H03F2200/451 , H03F2203/45034 , H03F2203/45058 , H03F2203/45138 , H03F2203/45296 , H03F2203/45301 , H03F2203/45316 , H03F2203/45396 , H03F2203/7239 , H03G1/0017 , H03G1/0029 , H03G1/0088 , H03G3/3052 , H03G3/3078
摘要： An amplifier with integrated filter (e.g., an LNA) is described. In one design, the amplifier may include a gain stage, a filter stage, and a buffer stage. The gain stage may provide signal amplification for an input signal. The filter stage may provide filtering for the input signal. The buffer stage may buffer a filtered signal from the filter stage. The amplifier may further include a second filter stage and a second buffer stage. The second filter stage may provide additional filtering for the input signal. The second buffer stage may buffer a second filtered signal from the second filter stage. All of the stages may be stacked and coupled between a supply voltage and circuit ground. The filter stage(s) may implement an elliptical lowpass filter. Each filter stage may include an inductor and a capacitor coupled in parallel and forming a resonator tank to attenuate interfering signals.
摘要翻译：描述了具有集成滤波器（例如，LNA）的放大器。在一种设计中，放大器可以包括增益级，滤波级和缓冲级。增益级可以为输入信号提供信号放大。滤波器级可以为输入信号提供滤波。缓冲级可以缓冲来自滤波级的滤波信号。放大器还可以包括第二滤波器级和第二缓冲级。第二滤波器级可以为输入信号提供额外的滤波。第二缓冲级可以缓冲来自第二滤波级的第二滤波信号。所有级可以堆叠并耦合在电源电压和电路接地之间。滤波器级可以实现椭圆形低通滤波器。每个滤波器级可以包括并联耦合的电感器和电容器，并形成谐振器箱以衰减干扰信号。

7. 发明授权

US08019310B2 Local oscillator buffer and mixer having adjustable size 有权
标题翻译：具有可调大小的本地振荡器缓冲器和混频器
公开(公告)号：US08019310B2
公开(公告)日：2011-09-13
申请号：US11955201
申请日：2007-12-12
申请人： Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
发明人： Gurkanwal Singh Sahota , Frederic Bossu , Ojas M. Choksi
IPC分类号： H04B1/26 , H04B7/00 , H04B15/00
CPC分类号： H03D7/1441 , H03D7/165 , H03D7/166 , H03D2200/0084 , H03D2200/009
摘要： Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an embodiment, LO buffer and/or mixer size may be increased when a receiver operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver operates in a low gain mode. In an embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific embodiments of LO buffers and mixers having adjustable size are disclosed.
摘要翻译：公开了本地振荡器（LO）缓冲器和混频器的可选尺寸。在一个实施例中，当接收机以高增益模式工作时，可以增加LO缓冲器和/或混频器的大小，而当接收器以低增益模式工作时，可以减小LO缓冲器和/或混频器的大小。在一个实施例中，LO缓冲器和混合器尺寸在锁定步骤中增加和减小。公开了具有可调节尺寸的LO缓冲器和混合器的具体实施例的电路拓扑和控制方案。

8. 发明授权

US07936217B2 High-linearity complementary amplifier 有权
标题翻译：高线性互补放大器
公开(公告)号：US07936217B2
公开(公告)日：2011-05-03
申请号：US11947570
申请日：2007-11-29
申请人： Junxiong Deng , Gurkanwal Singh Sahota , Solti Peng
发明人： Junxiong Deng , Gurkanwal Singh Sahota , Solti Peng
IPC分类号： H03F3/18
CPC分类号： H03F1/3205 , H03F1/0261 , H03F1/086 , H03F1/3211 , H03F1/56 , H03F3/19 , H03F3/3022 , H03F3/45179 , H03F2200/18 , H03F2200/294 , H03F2200/354 , H03F2200/451
摘要： A complementary amplifier includes an NMOS transistor coupled to a PMOS transistor in a stacked configuration. The NMOS transistor and the PMOS transistor receive and amplify an input signal. The NMOS and PMOS transistors operate as a linear complementary amplifier and provide an output signal. The NMOS and PMOS transistors may have separate bias voltages, which may be selected to overlap the low-to-high and high-to-low transitions of the transconductances of these transistors. The width and length dimensions of the NMOS and PMOS transistors may be selected to match the change in input capacitance and the change in transconductance of the NMOS transistor in moderate inversion region with the change in input capacitance and the change in transconductance of the PMOS transistor in moderate inversion region. The complementary amplifier may have an approximately constant total input capacitance and an approximately constant total transconductance over a range of voltages.
摘要翻译：互补放大器包括以堆叠配置耦合到PMOS晶体管的NMOS晶体管。 NMOS晶体管和PMOS晶体管接收和放大输入信号。 NMOS和PMOS晶体管作为线性互补放大器工作并提供输出信号。 NMOS和PMOS晶体管可以具有单独的偏置电压，其可以被选择为与这些晶体管的跨导的低到高和高到低的跃迁重叠。可以选择NMOS和PMOS晶体管的宽度和长度尺寸以匹配输入电容的变化和中等反转区中NMOS晶体管的跨导变化，随着输入电容的变化和PMOS晶体管的跨导变化中等反转区。互补放大器可以具有近似恒定的总输入电容和在一定范围的电压上的近似恒定的总跨导。

9. 发明申请

US20090175399A1 DIGITAL PHASE-LOCKED LOOP WITH GATED TIME-TO-DIGITAL CONVERTER 有权
标题翻译：数字锁相环与定位的时间到数字转换器
公开(公告)号：US20090175399A1
公开(公告)日：2009-07-09
申请号：US11969359
申请日：2008-01-04
申请人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
发明人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
IPC分类号： H03D3/24
CPC分类号： H03L7/0802 , H03L7/087
摘要： A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.
摘要翻译：数字PLL（DPLL）包括时间 - 数字转换器（TDC）和控制单元。定期启用TDC以持续短时间量化相位信息，并在剩余时间内禁用TDC以降低功耗。 TDC接收第一时钟信号和第一参考信号，并提供指示第一时钟信号和第一参考信号之间的相位差的TDC输出。控制单元基于主参考信号生成使能信号，并使能和禁止具有使能信号的TDC。在一种设计中，控制单元延迟主参考信号以获得第一参考信号和第二参考信号，基于主参考信号和第二参考信号产生使能信号，并且将主时钟信号与使能信号以获得TDC的第一个时钟信号。

10. 发明申请

US20090140812A1 HIGH-LINEARITY COMPLEMENTARY AMPLIFIER 有权
标题翻译：高线性互补放大器
公开(公告)号：US20090140812A1
公开(公告)日：2009-06-04
申请号：US11947570
申请日：2007-11-29
申请人： Junxiong Deng , Gurkanwal Singh Sahota , Solti Peng
发明人： Junxiong Deng , Gurkanwal Singh Sahota , Solti Peng
IPC分类号： H03F3/16
CPC分类号： H03F1/3205 , H03F1/0261 , H03F1/086 , H03F1/3211 , H03F1/56 , H03F3/19 , H03F3/3022 , H03F3/45179 , H03F2200/18 , H03F2200/294 , H03F2200/354 , H03F2200/451
摘要： A complementary amplifier includes an NMOS transistor coupled to a PMOS transistor in a stacked configuration. The NMOS transistor and the PMOS transistor receive and amplify an input signal. The NMOS and PMOS transistors operate as a linear complementary amplifier and provide an output signal. The NMOS and PMOS transistors may have separate bias voltages, which may be selected to overlap the low-to-high and high-to-low transitions of the transconductances of these transistors. The width and length dimensions of the NMOS and PMOS transistors may be selected to match the change in input capacitance and the change in transconductance of the NMOS transistor in moderate inversion region with the change in input capacitance and the change in transconductance of the PMOS transistor in moderate inversion region. The complementary amplifier may have an approximately constant total input capacitance and an approximately constant total transconductance over a range of voltages.
摘要翻译：互补放大器包括以堆叠配置耦合到PMOS晶体管的NMOS晶体管。 NMOS晶体管和PMOS晶体管接收和放大输入信号。 NMOS和PMOS晶体管作为线性互补放大器工作并提供输出信号。 NMOS和PMOS晶体管可以具有单独的偏置电压，其可以被选择为与这些晶体管的跨导的低到高和高到低的跃迁重叠。可以选择NMOS和PMOS晶体管的宽度和长度尺寸以匹配输入电容的变化和中等反转区中NMOS晶体管的跨导变化，随着输入电容的变化和PMOS晶体管的跨导变化中等反转区。互补放大器可以具有近似恒定的总输入电容和在一定范围的电压上的近似恒定的总跨导。

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