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1. 发明授权

US07973389B2 Isolated tri-gate transistor fabricated on bulk substrate 有权
标题翻译：在本体衬底上制造的隔离三栅极晶体管
公开(公告)号：US07973389B2
公开(公告)日：2011-07-05
申请号：US12590562
申请日：2009-11-10
申请人： Rafael Rios , Jack Kavalieros , Stephen M. Cea
发明人： Rafael Rios , Jack Kavalieros , Stephen M. Cea
IPC分类号： H01L21/02 , H01L29/06 , H01L29/41
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.
摘要翻译：形成隔离的三栅极半导体器件的方法包括：图案化块状衬底以形成翅片结构，在鳍结构周围沉积绝缘材料，使绝缘材料凹陷以暴露将用于三极管的鳍结构的一部分 - 半导体本体，在所述鳍结构的暴露部分上沉积氮化物帽以保护所述鳍结构的暴露部分，以及执行热氧化工艺以将所述鳍状结构的未受保护的部分氧化在所述氮化物帽下方。翅片的氧化部分隔离被氮化物盖保护的半导体主体。然后可以去除氮化物盖。热氧化过程可以包括在大约900℃和大约1100℃之间的温度下退火约0.5小时至约3小时的时间。

2. 发明申请

US20100059821A1 Isolated tri-gate transistor fabricated on bulk substrate 有权
标题翻译：在本体衬底上制造的隔离三栅极晶体管
公开(公告)号：US20100059821A1
公开(公告)日：2010-03-11
申请号：US12590562
申请日：2009-11-10
申请人： Rafael Rios , Jack Kavalieros , Stephen M. Cea
发明人： Rafael Rios , Jack Kavalieros , Stephen M. Cea
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.
摘要翻译：形成隔离的三栅极半导体器件的方法包括：图案化块状衬底以形成翅片结构，在鳍结构周围沉积绝缘材料，使绝缘材料凹陷以暴露将用于三极管的鳍结构的一部分 - 半导体本体，在所述鳍结构的暴露部分上沉积氮化物帽以保护所述鳍结构的暴露部分，以及执行热氧化工艺以将所述鳍状结构的未受保护的部分氧化在所述氮化物帽下方。翅片的氧化部分隔离被氮化物盖保护的半导体主体。然后可以去除氮化物盖。热氧化过程可以包括在大约900℃和大约1100℃之间的温度下退火约0.5小时至约3小时的时间。

3. 发明申请

US20090020792A1 ISOLATED TRI-GATE TRANSISTOR FABRICATED ON BULK SUBSTRATE 审中-公开
标题翻译：隔离三极晶体管在大块基板上制作
公开(公告)号：US20090020792A1
公开(公告)日：2009-01-22
申请号：US11779284
申请日：2007-07-18
申请人： Rafael Rios , Jack Kavalieros , Stephen M. Cea
发明人： Rafael Rios , Jack Kavalieros , Stephen M. Cea
IPC分类号： H01L29/78 , H01L21/02
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.
摘要翻译：形成隔离的三栅极半导体器件的方法包括：图案化块状衬底以形成翅片结构，在鳍结构周围沉积绝缘材料，使绝缘材料凹陷以暴露将用于三极管的鳍结构的一部分 - 半导体本体，在所述鳍结构的暴露部分上沉积氮化物帽以保护所述鳍结构的暴露部分，以及执行热氧化工艺以将所述鳍状结构的未受保护的部分氧化在所述氮化物帽下方。翅片的氧化部分隔离被氮化物盖保护的半导体主体。然后可以去除氮化物盖。热氧化过程可以包括在大约900℃和大约1100℃之间的温度下退火约0.5小时至约3小时的时间。

4. 发明授权

US08753942B2 Silicon and silicon germanium nanowire structures 有权
标题翻译：硅和硅锗纳米线结构
公开(公告)号：US08753942B2
公开(公告)日：2014-06-17
申请号：US12958179
申请日：2010-12-01
申请人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
发明人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
IPC分类号： H01L29/775 , H01L29/66 , H01L21/336 , H01L21/762 , H01L29/772 , B82Y40/00
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/76224 , H01L27/0922 , H01L27/1203 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/165 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

5. 发明申请

US20120138886A1 SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES 有权
标题翻译：硅和硅锗纳米结构
公开(公告)号：US20120138886A1
公开(公告)日：2012-06-07
申请号：US12958179
申请日：2010-12-01
申请人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
发明人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
IPC分类号： H01L29/775 , H01L29/66 , H01L21/336 , H01L21/762 , B82Y40/00 , H01L29/772
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/76224 , H01L27/0922 , H01L27/1203 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/165 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

6. 发明授权

US09608059B2 Semiconductor device with isolated body portion 有权
公开(公告)号：US09608059B2
公开(公告)日：2017-03-28
申请号：US13995418
申请日：2011-12-20
申请人： Annalisa Cappellani , Stephen M. Cea , Tahir Ghani , Harry Gomez , Jack T. Kavalieros , Patrick H. Keys , Seiyon Kim , Kelin J. Kuhn , Aaron D. Lilak , Rafael Rios , Mayank Sahni
发明人： Annalisa Cappellani , Stephen M. Cea , Tahir Ghani , Harry Gomez , Jack T. Kavalieros , Patrick H. Keys , Seiyon Kim , Kelin J. Kuhn , Aaron D. Lilak , Rafael Rios , Mayank Sahni
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78 , H01L21/762 , H01L29/775 , H01L27/12 , B82Y10/00
CPC分类号： H01L29/66818 , B82Y10/00 , H01L21/762 , H01L21/76216 , H01L27/1203 , H01L29/0649 , H01L29/0653 , H01L29/0673 , H01L29/42392 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

7. 发明授权

US09583602B2 Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs 有权
标题翻译：用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法
公开(公告)号：US09583602B2
公开(公告)日：2017-02-28
申请号：US15209552
申请日：2016-07-13
申请人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
发明人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
IPC分类号： H01L29/66 , H01L29/78 , H01L29/739 , H01L29/16 , H01L29/161 , H01L29/06 , H01L29/24 , H01L29/267 , H01L27/092 , H01L29/04 , H01L29/10 , H01L29/165 , H01L29/20 , H01L29/423 , H01L29/786
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696
摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
摘要翻译：描述了用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法。例如，隧道场效应晶体管（TFET）包括设置在衬底上方的均质有源区。同质结有源区包括其中具有未掺杂沟道区的松弛Ge或GeSn体。同质结有源区还包括设置在放大的Ge或GeSn体中，在沟道区两侧的掺杂源极和漏极区。 TFET还包括设置在沟道区域之间的源极和漏极区域之间的栅极堆叠。栅极堆叠包括栅极电介质部分和栅极电极部分。

8. 发明申请

US20160322480A1 TUNNELING FIELD EFFECT TRANSISTORS (TFETS) FOR CMOS ARCHITECTURES AND APPROACHES TO FABRICATING N-TYPE AND P-TYPE TFETS 审中-公开
公开(公告)号：US20160322480A1
公开(公告)日：2016-11-03
申请号：US15209552
申请日：2016-07-13
申请人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, JR. , Ian A. Young , Kelin J. Kuhn
发明人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, JR. , Ian A. Young , Kelin J. Kuhn
IPC分类号： H01L29/66 , H01L29/06 , H01L29/165 , H01L27/092 , H01L29/161 , H01L29/10 , H01L29/20 , H01L29/04 , H01L29/786 , H01L29/423
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696
摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

9. 发明授权

US09224810B2 CMOS nanowire structure 有权
标题翻译： CMOS纳米线结构
公开(公告)号：US09224810B2
公开(公告)日：2015-12-29
申请号：US13996503
申请日：2011-12-23
申请人： Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Annalisa Cappellani , Stephen M. Cea , Rafael Rios , Glenn A. Glass
发明人： Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Annalisa Cappellani , Stephen M. Cea , Rafael Rios , Glenn A. Glass
IPC分类号： H01L29/06 , H01L21/8238 , H01L27/092 , H01L27/12 , B82Y10/00 , H01L29/66 , H01L29/775
CPC分类号： H01L21/823821 , B82Y10/00 , H01L21/8238 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L21/845 , H01L27/092 , H01L27/0924 , H01L27/12 , H01L27/1203 , H01L27/1211 , H01L29/0673 , H01L29/0676 , H01L29/1033 , H01L29/42356 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/7853
摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.
摘要翻译：描述了免费的金属氧化物半导体纳米线结构。例如，半导体结构包括第一半导体器件。第一半导体器件包括设置在衬底之上的第一纳米线。第一纳米线具有在衬底上方的第一距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。第一栅极电极堆叠完全包围第一纳米线的离散通道区域。半导体结构还包括第二半导体器件。第二半导体器件包括设置在衬底上方的第二纳米线。第二纳米线在衬底上方具有第二距离的中点，并且在离散通道区域的任一侧上包括离散通道区域和源极和漏极区域。第一距离与第二距离不同。第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。

10. 发明授权

US09129829B2 Silicon and silicon germanium nanowire structures 有权
标题翻译：硅和硅锗纳米线结构
公开(公告)号：US09129829B2
公开(公告)日：2015-09-08
申请号：US14274592
申请日：2014-05-09
申请人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
发明人： Kelin J. Kuhn , Seiyon Kim , Rafael Rios , Stephen M. Cea , Martin D. Giles , Annalisa Cappellani , Titash Rakshit , Peter Chang , Willy Rachmady
IPC分类号： H01L29/165 , H01L29/06 , B82Y10/00 , H01L21/762 , H01L29/16 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/78 , H01L29/786
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/76224 , H01L27/0922 , H01L27/1203 , H01L29/0676 , H01L29/1033 , H01L29/16 , H01L29/165 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66795 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。

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