专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08196124B2 SIMD code generation in the presence of optimized misaligned data reorganization 失效
标题翻译：存在优化的未对齐数据重组的SIMD代码生成
公开(公告)号：US08196124B2
公开(公告)日：2012-06-05
申请号：US12196764
申请日：2008-08-22
申请人： Alexandre E. Eichenberger , Kai-Ting Amy Wang , Peng Wu
发明人： Alexandre E. Eichenberger , Kai-Ting Amy Wang , Peng Wu
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F8/447
摘要： Loop code is generated to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop operates on datatypes having different lengths. Further, a preferred embodiment of the present invention includes a novel technique to efficiently realign or shift arbitrary streams to an arbitrary offset, regardless whether the alignments or offsets are known at the compile time or not. This technique enables the application of advanced alignment optimizations to runtime alignment. This allows sequential loop code operating on datatypes of disparate length to be transformed (“simdized”) into optimized SIMD code through a fully automated process.
摘要翻译：生成循环代码以在单指令多数据路径（SIMD）架构上执行，其中循环对具有不同长度的数据类型进行操作。此外，本发明的优选实施例包括一种用于有效地将任意流重新对准或将任意流移动到任意偏移的新技术，无论在编译时是否已知对准或偏移。这种技术使得可以将高级对齐优化应用于运行时对齐。这允许对具有不同长度的数据类型的顺序循环代码通过完全自动化的过程进行转换（“模拟化”）成优化的SIMD代码。

12. 发明申请

US20110276786A1 Shared Prefetching to Reduce Execution Skew in Multi-Threaded Systems 失效
标题翻译：共享预取以减少多线程系统中的执行偏差
公开(公告)号：US20110276786A1
公开(公告)日：2011-11-10
申请号：US12773454
申请日：2010-05-04
申请人： Alexandre E. Eichenberger , John A. Gunnels
发明人： Alexandre E. Eichenberger , John A. Gunnels
IPC分类号： G06F9/30 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F8/4442 , G06F9/30047 , G06F9/383 , G06F9/3851 , G06F2212/6028
摘要： Mechanisms are provided for optimizing code to perform prefetching of data into a shared memory of a computing device that is shared by a plurality of threads that execute on the computing device. A memory stream of a portion of code that is shared by the plurality of threads is identified. A set of prefetch instructions is distributed across the plurality of threads. Prefetch instructions are inserted into the instruction sequences of the plurality of threads such that each instruction sequence has a separate sub-portion of the set of prefetch instructions, thereby generating optimized code. Executable code is generated based on the optimized code and stored in a storage device. The executable code, when executed, performs the prefetches associated with the distributed set of prefetch instructions in a shared manner across the plurality of threads.
摘要翻译：提供了用于优化代码以执行数据预取到由计算设备上执行的多个线程共享的计算设备的共享存储器的机制。识别由多个线程共享的代码的一部分的存储器流。一组预取指令分布在多个线程上。预取指令被插入到多个线程的指令序列中，使得每个指令序列具有预取指令集合的单独的子部分，从而生成优化的代码。可执行代码基于优化的代码生成并存储在存储设备中。执行的可执行代码在多个线程中以共享的方式执行与分布式预取指令集相关联的预取。

13. 发明申请

US20110219208A1 MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER 有权
标题翻译：多层高效平行超级计算机
公开(公告)号：US20110219208A1
公开(公告)日：2011-09-08
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

14. 发明申请

US20110161643A1 Runtime Extraction of Data Parallelism 有权
标题翻译：数据并行性的运行时提取
公开(公告)号：US20110161643A1
公开(公告)日：2011-06-30
申请号：US12649860
申请日：2009-12-30
申请人： Alexandre E. Eichenberger , Brian K. Flachs , Charles R. Johns , Mark R. Nutter
发明人： Alexandre E. Eichenberger , Brian K. Flachs , Charles R. Johns , Mark R. Nutter
IPC分类号： G06F9/32
CPC分类号： G06F9/3887 , G06F8/4441 , G06F9/381 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/3859
摘要： Mechanisms for extracting data dependencies during runtime are provided. The mechanisms execute a portion of code having a loop and generate, for the loop, a first parallel execution group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The mechanisms further execute the first parallel execution group and determining, for each iteration in the subset of iterations, whether the iteration has a data dependence. Moreover, the mechanisms commit store data to system memory only for stores performed by iterations in the subset of iterations for which no data dependence is determined. Store data of stores performed by iterations in the subset of iterations for which a data dependence is determined is not committed to the system memory.
摘要翻译：提供了在运行时提取数据依赖关系的机制。所述机制执行具有循环的一部分代码，并为所述循环生成包括小于所述循环的总迭代次数的循环迭代子集的第一并行执行组。机制进一步执行第一个并行执行组，并确定迭代子集中的每个迭代，迭代是否具有数据依赖性。此外，机制仅将数据存储到系统存储器中，用于仅在确定了数据依赖性的迭代子集中通过迭代执行的存储。在确定数据相关性的迭代子集中存储由迭代执行的存储数据不会提交给系统存储器。

15. 发明申请

US20110047362A1 Version Pressure Feedback Mechanisms for Speculative Versioning Caches 失效
标题翻译：版本控制缓存的版本压力反馈机制
公开(公告)号：US20110047362A1
公开(公告)日：2011-02-24
申请号：US12543688
申请日：2009-08-19
申请人： Alexandre E. Eichenberger , Alan Gara , Kathryn M. O'Brien , Martin Ohmacht , Xiaotong Zhuang
发明人： Alexandre E. Eichenberger , Alan Gara , Kathryn M. O'Brien , Martin Ohmacht , Xiaotong Zhuang
IPC分类号： G06F12/08 , G06F9/318
CPC分类号： G06F9/3851 , G06F9/3885 , G06F12/0842
摘要： Mechanisms are provided for controlling version pressure on a speculative versioning cache. Raw version pressure data is collected based on one or more threads accessing cache lines of the speculative versioning cache. One or more statistical measures of version pressure are generated based on the collected raw version pressure data. A determination is made as to whether one or more modifications to an operation of a data processing system are to be performed based on the one or more statistical measures of version pressure, the one or more modifications affecting version pressure exerted on the speculative versioning cache. An operation of the data processing system is modified based on the one or more determined modifications, in response to a determination that one or more modifications to the operation of the data processing system are to be performed, to affect the version pressure exerted on the speculative versioning cache.
摘要翻译：提供了用于控制推测版本缓存的版本压力的机制。基于访问推测性版本缓存的高速缓存行的一个或多个线程来收集原始版本压力数据。基于收集的原始版本压力数据生成版本压力的一个或多个统计度量。确定是否将基于版本压力的一个或多个统计测量来执行对数据处理系统的操作的一个或多个修改，该一个或多个修改影响施加在推测版本缓存上的版本压力。响应于将要执行对数据处理系统的操作的一个或多个修改以影响施加在投机上的版本压力的确定，基于一个或多个确定的修改来修改数据处理系统的操作版本缓存。

16. 发明申请

US20110047359A1 Insertion of Operation-and-Indicate Instructions for Optimized SIMD Code 有权
标题翻译：插入优化SIMD代码的操作指示说明
公开(公告)号：US20110047359A1
公开(公告)日：2011-02-24
申请号：US12543628
申请日：2009-08-19
申请人： Alexandre E. Eichenberger , Alan Gara , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Alan Gara , Michael K. Gschwind
IPC分类号： G06F9/45 , G06F9/302
CPC分类号： G06F8/451 , G06F9/30036 , G06F9/30043 , G06F9/3865 , G06F9/3887
摘要： Mechanisms are provided for inserting indicated instructions for tracking and indicating exceptions in the execution of vectorized code. A portion of first code is received for compilation. The portion of first code is analyzed to identify non-speculative instructions performing designated non-speculative operations in the first code that are candidates for replacement by replacement operation-and-indicate instructions that perform the designated non-speculative operations and further perform an indication operation for indicating any exception conditions corresponding to special exception values present in vector register inputs to the replacement operation-and-indicate instructions. The replacement is performed and second code is generated based on the replacement of the at least one non-speculative instruction. The data processing system executing the compiled code is configured to store special exception values in vector output registers, in response to a speculative instruction generating an exception condition, without initiating exception handling.
摘要翻译：提供了用于在执行向量化代码中插入指示的跟踪指示和指示异常的机制。第一个代码的一部分被接收用于编译。对第一代码的部分进行分析，以识别在第一代码中执行指定的非推测操作的非推测指令，该第一代码是通过替换操作指示执行指定的非推测操作的指令进行替换的候补，并进一步执行指示操作用于指示对应于向量寄存器输入中存在的替换操作和指示指令的特殊异常值的任何异常条件。执行替换，并且基于替换至少一个非推测性指令来生成第二代码。执行编译代码的数据处理系统被配置为在矢量输出寄存器中存储特殊异常值，以响应于产生异常条件的推测指令，而不启动异常处理。

17. 发明授权

US07673284B2 Method and system for versioning codes based on relative alignment for single instruction multiple data units 失效
标题翻译：基于单指令多数据单元相对对齐的版本编码方法和系统
公开(公告)号：US07673284B2
公开(公告)日：2010-03-02
申请号：US11333614
申请日：2006-01-17
申请人： Alexandre E. Eichenberger , Amy (K. T.) Wang , Peng Wu , Peng Zhao
发明人： Alexandre E. Eichenberger , Amy (K. T.) Wang , Peng Wu , Peng Zhao
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/49
摘要： A method and system for generating efficient versioned codes for single instruction multiple data units whose memory systems have alignment constraints. The system creates multiple versions of codes based on relative alignments of the data streams involved in the computation. The system also analyzes characteristics of relative alignments (e.g. compile-time or runtime) to determine whether code versioning is beneficial based on a cost model.
摘要翻译：一种用于为存储器系统具有对准约束的单指令多数据单元生成有效版本代码的方法和系统。该系统基于计算中涉及的数据流的相对对齐来创建多个版本的代码。系统还分析相对比对的特征（例如编译时或运行时），以确定代码版本化是否基于成本模型是有益的。

18. 发明申请

US20090307656A1 Optimized Scalar Promotion with Load and Splat SIMD Instructions 失效
标题翻译：通过加载和Splat SIMD指令优化标量升级
公开(公告)号：US20090307656A1
公开(公告)日：2009-12-10
申请号：US12134495
申请日：2008-06-06
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels
IPC分类号： G06F9/44
CPC分类号： G06F8/45
摘要： Mechanisms for optimizing scalar code executed on a single instruction multiple data (SIMD) engine are provided. Placement of vector operation-splat operations may be determined based on an identification of scalar and SIMD operations in an original code representation. The original code representation may be modified to insert the vector operation-splat operations based on the determined placement of vector operation-splat operations to generate a first modified code representation. Placement of separate splat operations may be determined based on identification of scalar and SIMD operations in the first modified code representation. The first modified code representation may be modified to insert or delete separate splat operations based on the determined placement of the separate splat operations to generate a second modified code representation. SIMD code may be output based on the second modified code representation for execution by the SIMD engine.
摘要翻译：提供了在单指令多数据（SIMD）引擎上执行的优化标量代码的机制。可以基于原始代码表示中的标量和SIMD操作的标识来确定矢量操作 - 拼接操作的放置。可以修改原始代码表示以基于所确定的向量操作 - 分组操作的放置来插入向量操作 - 拼接操作以生成第一修改代码表示。可以基于第一修改代码表示中的标量和SIMD操作的标识来确定单独的拼接操作的放置。可以修改第一修改代码表示以基于确定的单独splat操作的布局来插入或删除单独的splat操作以生成第二修改代码表示。可以基于SIMD引擎执行的第二修改代码表示来输出SIMD代码。

19. 发明申请

US20090248985A1 Data Transfer Optimized Software Cache for Regular Memory References 有权
标题翻译：数据传输优化的软件缓存用于常规内存引用
公开(公告)号：US20090248985A1
公开(公告)日：2009-10-01
申请号：US12057447
申请日：2008-03-28
申请人： Eduard Ayguade , Tong Chen , Alexandre E. Eichenberger , Marc Gonzalez Tallada , Xavier Martorell , John K. O'Brien , Kathryn M. O'Brien , Zehra N. Sura , Tao Zhang
发明人： Eduard Ayguade , Tong Chen , Alexandre E. Eichenberger , Marc Gonzalez Tallada , Xavier Martorell , John K. O'Brien , Kathryn M. O'Brien , Zehra N. Sura , Tao Zhang
IPC分类号： G06F12/08
CPC分类号： G06F12/0837 , G06F8/4442 , G06F12/0848
摘要： Mechanisms are provided for optimizing regular memory references in computer code. These mechanisms may parse the computer code to identify memory references in the computer code. These mechanisms may further classify the memory references in the computer code as either regular memory references or irregular memory references. Moreover, the mechanisms may transform the computer code, by a compiler, to generate transformed computer code in which regular memory references access a storage of a software cache of a data processing system through a high locality cache mechanism of the software cache.
摘要翻译：提供机制用于优化计算机代码中的常规内存引用。这些机制可能解析计算机代码以识别计算机代码中的内存引用。这些机制可以将计算机代码中的存储器引用进一步分类为常规存储器引用或不规则存储器引用。此外，机制可以通过编译器转换计算机代码，以生成转换的计算机代码，其中常规内存引用通过软件高速缓存的高位置缓存机制访问数据处理系统的软件高速缓存的存储。

20. 发明申请

US20090064152A1 SYSTEMS, METHODS AND COMPUTER PRODUCTS FOR CROSS-THREAD SCHEDULING 有权
标题翻译：用于交叉螺纹调度的系统，方法和计算机产品
公开(公告)号：US20090064152A1
公开(公告)日：2009-03-05
申请号：US11847556
申请日：2007-08-30
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels , James L. McInnes , Mark P. Mendell
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels , James L. McInnes , Mark P. Mendell
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F8/445 , G06F9/3885
摘要： Systems, methods and computer products for cross-thread scheduling. Exemplary embodiments include a cross thread scheduling method for compiling code, the method including scheduling a scheduling unit with a scheduler sub-operation in response to the scheduling unit being in a non-multithreaded part of the code and scheduling the scheduling unit with a cross-thread scheduler sub-operation in response to the scheduling unit being in a multithreaded part of the code.
摘要翻译：用于跨线程调度的系统，方法和计算机产品。示例性实施例包括用于编译代码的交叉线程调度方法，所述方法包括：响应于所述调度单元处于所述代码的非多线程部分中的调度器子操作来调度调度单元，并且调度所述调度单元，响应于调度单元处于代码的多线程部分中的线程调度器子操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式