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    • 11. 发明申请
    • Digital audio broadcast receiver
    • 数字音频广播接收机
    • US20080152049A1
    • 2008-06-26
    • US11953674
    • 2007-12-10
    • Harald SandnerAjaib Hussain
    • Harald SandnerAjaib Hussain
    • H04L27/06
    • H04L27/0014H04H40/18H04H2201/20
    • A digital audio broadcast (DAB) receiver (10) for receiving an RF signal comprises a low noise amplifier (16), an RF mixer (24) that generates an intermediate frequency signal, and a voltage controlled oscillator (23). The receiver includes a tracking filter (18) downstream of the low noise amplifier (16) and upstream of the RF mixer (24), wherein the tracking filter is tuned to track a selected channel frequency out of the received RF signal. In a described embodiment, the tracking filter includes a bandpass filter (20) and a notch filter (22). A center frequency of the bandpass filter is tuned to track the selected channel frequency; and an attenuation notch of the notch filter is tuned to track a frequency which is separated from the selected channel frequency by a fixed frequency; the attenuation notch of the notch filter is tuned together with the center frequency of the bandpass filter, and the center frequencies of the notch filter and the bandpass filter are separated by a fixed frequency. The tracking filter is tuned by a digital word developed by a digital signal processor responsive to the intermediate frequency signal.
    • 用于接收RF信号的数字音频广播(DAB)接收机(10)包括低噪声放大器(16),产生中频信号的RF混频器(24)和压控振荡器(23)。 接收器包括在低噪声放大器(16)下游和RF混频器(24)的上游的跟踪滤波器(18),其中跟踪滤波器被调谐以跟踪所接收的RF信号中所选择的信道频率。 在所描述的实施例中,跟踪滤波器包括带通滤波器(20)和陷波滤波器(22)。 调整带通滤波器的中心频率以跟踪所选择的信道频率; 并且陷波滤波器的衰减陷波被调谐以跟踪与所选频道频率分离固定频率的频率; 陷波滤波器的衰减陷波与带通滤波器的中心频率一起调谐,陷波滤波器和带通滤波器的中心频率以固定频率分开。 跟踪滤波器由响应于中频信号的数字信号处理器开发的数字字来调谐。
    • 12. 发明授权
    • Phase locked loop with two-step control
    • 具有两步控制的锁相环
    • US07724093B2
    • 2010-05-25
    • US12139291
    • 2008-06-13
    • Alexander WormerHarald Sandner
    • Alexander WormerHarald Sandner
    • H03L7/085H03L7/089H03L7/099
    • H03L7/113H03L7/087H03L7/089H03L7/093H03L7/0991H03L7/18H03L2207/50
    • A phase locked loop has a digitally controlled oscillator (DCO) for generating a DCO output signal (fOSC), a clock divider coupled to the DCO and receiving the DCO output signal and outputting a feedback clock signal (fN), and a phase frequency detector (PFD) coupled to the DCO and controlling the DCO by a DCO control signal (dCNTL). The PFD has a first input for receiving the feedback clock signal (fN), a second input for receiving a reference clock signal (fREF), and comprises a frequency detection stage (FD) adapted to calculate a frequency difference between the feedback clock signal (fN) and the reference clock signal (fREF) in a frequency detection mode and to adjust the DCO control signal based on said frequency difference, a phase detection (PD) stage for calculating a phase error between the feedback clock signal and the reference clock signal in a phase detection mode, and a switch for switching between the frequency detection mode and the phase detection mode upon the frequency of the feedback clock signal reaching a predetermined value.
    • 锁相环具有用于产生DCO输出信号(fOSC)的数字控制振荡器(DCO),耦合到DCO并接收DCO输出信号并输出​​反馈时钟信号(fN)的时钟分频器,以及相位频率检测器 (PFD)耦合到DCO并通过DCO控制信号(dCNTL)控制DCO。 PFD具有用于接收反馈时钟信号(fN)的第一输入端,用于接收基准时钟信号(fREF)的第二输入端,并且包括频率检测级(FD),该频率检测级适于计算反馈时钟信号 fN)和参考时钟信号(fREF),并且基于所述频率差调整DCO控制信号;相位检测(PD)级,用于计算反馈时钟信号和参考时钟信号之间的相位误差 在相位检测模式中,以及用于在反馈时钟信号的频率达到预定值时在频率检测模式和相位检测模式之间切换的开关。
    • 13. 发明授权
    • All digital phase locked loop system and method
    • 所有数字锁相环系统及方法
    • US07605664B2
    • 2009-10-20
    • US11624149
    • 2007-01-17
    • Harald SandnerHarald Parzhuber
    • Harald SandnerHarald Parzhuber
    • H03L7/085
    • H03L7/08H03L2207/50
    • An all digital PLL system generates an analog oscillator signal at intermediate frequencies to achieve averaged oscillator frequencies at an extremely high frequency resolution. The PLL system includes a digitally controlled oscillator (10) with a digital control input and an analog signal output, and a feedback loop with a digital loop filter (16) for generating a digital control signal for the digitally controlled oscillator (10). The digital loop filter (16) has a first output providing an integer part (nint) of the digital control signal and a second output providing a fractional part (nΣΔ) of the digital control signal. A sigma-delta modulator (14) has an input connected to the second output of the digital loop filter (16) and an output providing a one-bit digital output signal (ΣΔ), and a digital adder (12) has a first input connected to the first output of the digital loop filter (16), a second input connected to the output of the sigma-delta modulator (14), and an output connected to the digital control input of the digitally controlled oscillator (10). The output of the sigma-delta modulator (14) modulates the least significant bits from the first output of the digital loop filter (16).
    • 全数字PLL系统在中频产生模拟振荡器信号,以极高频率分辨率实现平均振荡器频率。 PLL系统包括具有数字控制输入和模拟信号输出的数字控制振荡器(10)和具有数字环路滤波器(16)的反馈回路,用于产生数字控制振荡器(10)的数字控制信号。 数字环路滤波器(16)具有提供数字控制信号的整数部分(nint)的第一输出和提供数字控制信号的小数部分(nSigmaDelta)的第二输出。 Σ-Δ调制器(14)具有连接到数字环路滤波器(16)的第二输出的输入端和提供一比特数字输出信号(SigmaDelta)的输出,数字加法器(12)具有第一输入 连接到数字环路滤波器(16)的第一输出,连接到Σ-Δ调制器(14)的输出端的第二输入端和连接到数字控制振荡器(10)的数字控制输入端的输出端。 Σ-Δ调制器(14)的输出调制来自数字环路滤波器(16)的第一输出的最低有效位。
    • 14. 发明申请
    • PHASE LOCKED LOOP WITH TWO-STEP CONTROL
    • 两相控制的锁相环
    • US20080309421A1
    • 2008-12-18
    • US12139291
    • 2008-06-13
    • Alexander WormerHarald Sandner
    • Alexander WormerHarald Sandner
    • H03L7/085
    • H03L7/113H03L7/087H03L7/089H03L7/093H03L7/0991H03L7/18H03L2207/50
    • A phase locked loop has a digitally controlled oscillator (DCO) for generating a DCO output signal (fOSC), a clock divider coupled to the DCO and receiving the DCO output signal and outputting a feedback clock signal (fN), and a phase frequency detector (PFD) coupled to the DCO and controlling the DCO by a DCO control signal (dCNTL). The PFD has a first input for receiving the feedback clock signal (fN), a second input for receiving a reference clock signal (fREF), and comprises a frequency detection stage (FD) adapted to calculate a frequency difference between the feedback clock signal (fN) and the reference clock signal (fREF) in a frequency detection mode and to adjust the DCO control signal based on said frequency difference, a phase detection (PD) stage for calculating a phase error between the feedback clock signal and the reference clock signal in a phase detection mode, and a switch for switching between the frequency detection mode and the phase detection mode upon the frequency of the feedback clock signal reaching a predetermined value.
    • 锁相环具有用于产生DCO输出信号(fOSC)的数字控制振荡器(DCO),耦合到DCO并接收DCO输出信号并输出​​反馈时钟信号(fN)的时钟分频器,以及相位频率检测器 (PFD)耦合到DCO并通过DCO控制信号(dCNTL)控制DCO。 PFD具有用于接收反馈时钟信号(fN)的第一输入端,用于接收基准时钟信号(fREF)的第二输入端,并且包括频率检测级(FD),该频率检测级适于计算反馈时钟信号 fN)和参考时钟信号(fREF),并且基于所述频率差调整DCO控制信号;相位检测(PD)级,用于计算反馈时钟信号和参考时钟信号之间的相位误差 在相位检测模式中,以及用于在反馈时钟信号的频率达到预定值时在频率检测模式和相位检测模式之间切换的开关。
    • 18. 发明申请
    • Prescaler for a phase-locked loop circuit
    • 预分频器用于锁相环电路
    • US20060071717A1
    • 2006-04-06
    • US11219989
    • 2005-09-06
    • Abdelghani El-KacimiHarald Sandner
    • Abdelghani El-KacimiHarald Sandner
    • H03L7/00
    • H03L7/081H03K21/02H03L7/18
    • A prescaler (10; 110) for use in a phase locked loop circuit, having a signal input (12; 112) receiving a digital input signal (SIG_IN) and a signal output (14; 114) supplying a digital output signal (SIG_OUT). A phase shifter (20; 120) receives an input signal from the signal input (12; 112), and supplies a set of n metasignals (METAk; METAI, METAQ, METAIN, METAQN) each having a relative phase shift of 2π/n with respect to another one of these metasignals. A phase selector (22; 122) has n inputs (34; 134I, 134Q, 134IN, 134QN) to each of which is applied a different one of the metasignals (METAk; METAI, METAQ, METAIN, METAQN) and an output (36; 136) that supplies a selected one of the metasignals. A final frequency divider (26; 126) has an input (70; 170) connected to the output (36; 136) of the phase selector (22; 122) and an output (72; 172) forming the signal output (14; 114) of the prescaler. A control circuit (60; 160) is associated with the phase selector (22; 122) and controls the phase selector so that the output (36; 136) of the phase selector is switched between different metasignals only when these different metasignals are in the same logical state, thereby avoiding the occurrence of glitches that would cause a frequency divider to miscount.
    • 一种用于锁相环电路的预分频器(10; 110),具有接收数字输入信号(SIG_IN)的信号输入端(12; 112)和提供数字输出信号(SIG_OUT)的信号输出端(14; 114) 。 移相器(20; 120)从信号输入端(12; 112)接收输入信号,并提供一组n个元信号(META>; META< I> 相对于这些异信号中的另一个,分别具有2pi / n的相对相移的元件,元件,元件,元件,元件QN。 相位选择器(22; 122)具有n个输入端(34; 134 I,134 Q,134 IN,134 QN),其中每一个输入端分别用不同的一个元信号(META> 和一个输出(36; 136),其输出(36; 136),其提供一个或多个 选择了一种元信号。 最终分频器(26; 126)具有连接到相位选择器(22; 122)的输出端(36; 136)的输入端(70; 170)和形成信号输出端的输出端(72; 172) 114)的预分频器。 控制电路(60; 160)与相位选择器(22; 122)相关联并且控制相位选择器,使得相位选择器的输出(36; 136)只有当这些不同的信号处于 相同的逻辑状态,从而避免发生会导致分频器错误计数的毛刺。
    • 19. 发明授权
    • Table tennis rubber solvent and adhesive systems
    • US5910528A
    • 1999-06-08
    • US826163
    • 1997-03-27
    • Waqidi FalicoffHarald Sandner
    • Waqidi FalicoffHarald Sandner
    • C08J5/12C08J7/00C08K5/10
    • C08J5/122C08J2321/00
    • Solvent systems, and adhesive systems comprising such solvent systems, primarily for use in forming speed-glued table tennis rackets are described. One embodiment of the solvent systems comprises a cycloalkane having from about 3 to about 10 carbon atoms, an ester having from about 2 to about 10 carbon atoms, and a terpene having a molecular weight of from about 110 to about 160. The cycloalkane generally is selected from the group consisting of cyclopentane, cyclohexane, and cycloheptane, with cyclohexane being a currently preferred cycloalkane. A currently preferred ester is ethyl acetate, and a currently preferred terpene is limonene. The solvent system also may comprise an ether, and preferred ethers are dipropylene glycol dimethyl ether and propylene glycol methyl ether acetate. The solvent system also can include an aliphatic alkane having about 10 carbon atoms or fewer, the aliphatic alkane being used in sufficient quantity to adjust the vapor pressure of the solvent system to be from about 50 mm/Hg to about 100 mm/Hg at 25.degree. C. Examples of suitable aliphatic alkanes are heptane, 2,2,4-trimethylpentane and mixtures thereof. The present invention also provides adhesive systems for use in forming speed-glued table tennis rackets. The adhesive system comprises the solvent systems described above, and from about 2 to about 10 weight percent of a solid or solids suitable for speed gluing table tennis rubbers to table tennis blades. A method for speed gluing a table tennis racket also is described. The method generally comprises forming a solvent or adhesive system as discussed above. The solvent or adhesive system is then applied to a table tennis rubber, a table tennis blade, or both. The rubber is then attached to the blade to form a speed-glued table tennis racket. If just a solvent system is used, then the rubber and/or the blade must provide sufficient solid or solids to adhere the rubber to the blade.