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11. 发明授权

US08510354B1 Calculation of trigonometric functions in an integrated circuit device 有权
标题翻译：集成电路设备中三角函数的计算
公开(公告)号：US08510354B1
公开(公告)日：2013-08-13
申请号：US12722683
申请日：2010-03-12
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/00
CPC分类号： G06F7/548
摘要： Circuitry for computing on x and y datapaths a trigonometric function of an input on a z datapath includes a comparison element to determine that the input is at or above a threshold, or below the threshold. The circuitry also includes a first left-shifter for shifting the z datapath by a constant when the input is below the threshold, and a second left-shifter for shifting an initialization value of the x datapath when the input is below the threshold. The circuitry further includes a look-up table including inverse tangent values based on negative powers of 2, and based on negative powers of 2-plus-the-constant and shifted by the constant, for adding to/subtracting from the z datapath, shifters for right-shifting elements of the x and y datapaths by amounts incorporating the constant and respective predetermined shift amounts that are adjusted when the input is below the threshold.
摘要翻译：用于在x和y数据路径上进行计算的电路用于在z数据路径上输入的三角函数包括用于确定输入处于或高于阈值或低于阈值的比较元件。电路还包括用于当输入低于阈值时将z数据路径移位常数的第一左移位器和用于当输入低于阈值时移位x数据路径的初始值的第二左移位器。该电路还包括一个查找表，其包括基于2的负功率的反正切值，并且基于2-plus-the常数的负功率并且被该常数偏移，用于从z数据路径添加/减去移位器用于通过包含当输入低于阈值时调整的常数和相应的预定移位量的量来右移x和y数据通路的元件。

12. 发明授权

US08484275B1 Reordering discrete fourier transform outputs 有权
标题翻译：重新排列离散傅立叶变换输出
公开(公告)号：US08484275B1
公开(公告)日：2013-07-09
申请号：US11952717
申请日：2007-12-07
申请人： Martin Langhammer , Neil Kenneth Thorne
发明人： Martin Langhammer , Neil Kenneth Thorne
IPC分类号： G06F15/00
CPC分类号： G06F17/142
摘要： There is provided a method for generating a table for reordering the output of a Fourier transform, the Fourier transform being performed on a predefined number of input samples, the method comprising performing one or more decomposition stages on a sequence corresponding in number to the predefined number of input samples to form a representation of the output of the Fourier transform; wherein at least one of the decomposition stages comprises a composite operation that is equivalent to two or more operations; and rearranging the representation of the output of the Fourier transform to generate a reordering table.
摘要翻译：提供了一种用于生成用于对傅里叶变换的输出进行重新排序的表格的方法，所述傅立叶变换是在预定数量的输入样本上执行的，所述方法包括在与预定数量相对应的序列上执行一个或多个分解阶段的输入样本以形成傅里叶变换的输出的表示; 其中所述分解阶段中的至少一个包括等效于两个或更多个操作的复合操作; 并重新排列傅立叶变换的输出的表示以产生重排序表。

13. 发明申请

US20120233230A1 DOUBLE-CLOCKED SPECIALIZED PROCESSING BLOCK IN AN INTEGRATED CIRCUIT DEVICE 有权
标题翻译：集成电路设备中的双时钟专用处理块
公开(公告)号：US20120233230A1
公开(公告)日：2012-09-13
申请号：US13044680
申请日：2011-03-10
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/00
CPC分类号： G06F7/5324
摘要： Circuitry for increasing the precision of multipliers by a desired factor while limiting the increase in arithmetic complexity of the multiplier to that factor can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD). The smaller increase in arithmetic complexity, so that the increase is proportional to the increase in precision, rather than to the square of the increase in precision, is achieved by using specialized processing block components differently on alternating clock cycles. For example, to implement double precision, the same multiplier components are used in each of two clock cycles, but some specialized processing block internal structures (e.g., shifters and adders) are used differently in the two cycles, so that over the two cycles, a larger multiplication may be calculated from smaller partial products.
摘要翻译：可以在固定逻辑器件中提供用于将乘法器的精度提高所需因数的电路，同时将乘法器的算术复杂度的增加限制为固定逻辑器件，或者可以配置成可编程集成电路器件，例如可编程逻辑器件（ PLD）。算术复杂度的增加较小，因此，通过在交替的时钟周期中不同地使用专门的处理块组件来实现增加与精度的增加成比例，而不是精度增加的平方。例如，要实现双精度，在两个时钟周期的每一个中使用相同的乘法器组件，但是在两个周期中使用了一些专门的处理块内部结构（例如，移位器和加法器），因此在两个周期中，可以从较小的部分乘积计算较大的乘积。

14. 发明授权

US08209545B1 FPGA configuration bitstream protection using multiple keys 有权
标题翻译： FPGA配置比特流保护使用多个密钥
公开(公告)号：US08209545B1
公开(公告)日：2012-06-26
申请号：US12785400
申请日：2010-05-21
申请人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
发明人： Martin Langhammer , Juju Joyce , Keone Streicher , David Jefferson , Srinivas Reddy , Nitin Prasad
IPC分类号： H04L9/08
CPC分类号： H04L9/065 , G06F21/60 , G06F21/76 , H04L9/0877 , H04L9/14 , H04L2209/12 , H04L2209/16 , H04L2209/26
摘要： Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.
摘要翻译：阻止检测和擦除编码或加密密钥的电路，方法和装置。这些编码密钥可以用于对配置比特流或FPGA或其他设备的其他数据进行编码。本发明的示例性实施例掩蔽第一密钥以形成编码密钥，以便防止第一密钥的检测。在具体实施例中，使用第二密钥对第一密钥进行编码。编码密钥用于对配置比特流或其他数据进行编码。编码密钥存储在FPGA或其他设备上。当要配置设备时，将检索编码密钥并将其用于解码比特流或其他数据。另一实施例将加密密钥存储在一次性可编程存储器（OTP）阵列中以防止其擦除或修改。在存储之前可以进一步模糊编码密钥。

15. 发明授权

US07984292B1 FPGA configuration bitstream encryption using modified key 有权
标题翻译： FPGA配置比特流加密使用修改密钥
公开(公告)号：US07984292B1
公开(公告)日：2011-07-19
申请号：US12559287
申请日：2009-09-14
申请人： Keone Streicher , David Jefferson , Juju Joyce , Martin Langhammer
发明人： Keone Streicher , David Jefferson , Juju Joyce , Martin Langhammer
IPC分类号： H04L29/06 , G06F15/16
CPC分类号： H04L9/0822 , H04L9/0631 , H04L9/065 , H04L9/0861 , H04L2209/24
摘要： Circuits, methods, and apparatus that prevent detection and erasure of a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a user key in order to prevent its detection. In a specific embodiment, the user key is masked by software that performs a function on it a first number of times. The result is used to encrypt a configuration bitstream. The user key is also provided to an FPGA or other device, where the function is performed a second number of times and the result stored. When the device is configured, the result is retrieved, the function is performed on it the first number of times less the second number of times and then it is used to decrypt the configuration bitstream. A further embodiment uses a one-time programmable fuse (OTP) array to prevent erasure or modification.
摘要翻译：阻止对FPGA或其他设备的配置比特流或其他数据的检测和擦除的电路，方法和装置。本发明的示例性实施例掩盖用户密钥以防止其检测。在具体实施例中，用户密钥被第一次执行功能的软件掩码。结果用于加密配置比特流。用户密钥还提供给FPGA或其他设备，其中功能被执行第二次并且存储结果。当配置设备时，将检索结果，该功能在其上执行第一次次数少于第二次，然后用于解密配置比特流。另一实施例使用一次性可编程熔丝（OTP）阵列来防止擦除或修改。

16. 发明授权

US07822799B1 Adder-rounder circuitry for specialized processing block in programmable logic device 有权
标题翻译：用于可编程逻辑器件中专用处理块的加法器电路
公开(公告)号：US07822799B1
公开(公告)日：2010-10-26
申请号：US11426403
申请日：2006-06-26
申请人： Martin Langhammer , Triet M. Nguyen , Yi-Wen Lin
发明人： Martin Langhammer , Triet M. Nguyen , Yi-Wen Lin
IPC分类号： G06F7/38
CPC分类号： G06F7/509 , G06F7/49963 , G06F7/5016 , G06F7/508
摘要： Adder/rounder circuitry for use in a programmable logic device computes a rounded sum quickly, and ideally within one clock cycle. The rounding position is selectable within a range of bit positions. In an input stage, for each bit position in that range, bits from both addends and a rounding bit are processed, while for each bit position outside that range only bits from both addends are processed. The input stage processing aligns its output in a common format for bits within and outside the range. The input processing may include 3:2 compression for bit positions within the range and 2:2 compression for bit positions outside the range, so that further processing is performed for all bit positions on a sum vector and a carry vector. Computation of the sum proceeds substantially simultaneously with and without the rounding input, and rounding logic makes a selection later in the computation.
摘要翻译：用于可编程逻辑器件的加法器/圆形电路可以快速计算舍入的并且理想地在一个时钟周期内计算。舍入位置可在位位置范围内选择。在输入级中，对于该范围内的每个位位置，处理来自两个加数和舍入位的位，而对于该范围之外的每个位位置，只处理来自两个加数的位。输入级处理以范围内和外的位的通用格式对齐其输出。输入处理可以包括在该范围内的比特位置的3：2压缩，以及在该范围之外的比特位置的2：2压缩，使得对和矢量和进位向量的所有比特位置执行进一步的处理。总和的计算基本上与舍入输入同时进行，并且舍入逻辑在计算中稍后进行选择。

17. 发明授权

US07734043B1 Encryption key obfuscation and storage 失效
标题翻译：加密密钥模糊和存储
公开(公告)号：US07734043B1
公开(公告)日：2010-06-08
申请号：US11042032
申请日：2005-01-25
申请人： David Jefferson , Martin Langhammer , Keone Streicher , Juju Joyce
发明人： David Jefferson , Martin Langhammer , Keone Streicher , Juju Joyce
IPC分类号： G06F9/00 , H04K1/00 , G06F9/24
CPC分类号： G06F21/76 , H04L9/065 , H04L9/0894 , H04L2209/12 , H04L2209/16
摘要： Circuits, methods, and apparatus that prevent easy detection and erasure or modification of an encryption or encoding key. This key may be used to encode and decode a configuration bitstream for an FPGA or other programmable or configurable device. One embodiment of the present invention obfuscates a key then stores it in a memory array on an FPGA. This memory array may be a one-time programmable memory to prevent erasure or modification of the key. After retrieval from storage, a reverse or de-obfuscation is performed to recover the key. Further obfuscation may be achieved by proper layout of the relevant circuitry.
摘要翻译：防止容易检测和擦除或修改加密或编码密钥的电路，方法和装置。该密钥可用于编码和解码FPGA或其他可编程或可配置设备的配置比特流。本发明的一个实施例模糊一个密钥然后将其存储在FPGA上的存储器阵列中。该存储器阵列可以是一次性可编程存储器，以防止键的擦除或修改。在从存储器检索之后，执行反向或去混淆以恢复密钥。可以通过相关电路的适当布局来实现进一步的模糊化。

18. 发明授权

US07660841B2 Flexible accumulator in digital signal processing circuitry 失效
标题翻译：灵活的累加器在数字信号处理电路中
公开(公告)号：US07660841B2
公开(公告)日：2010-02-09
申请号：US10783789
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
发明人： Leon Zheng , Martin Langhammer , Nitin Prasad , Greg Starr , Chiao Kai Hwang , Kumara Tharmalingam
IPC分类号： G06F7/38
CPC分类号： G06F7/5443 , G06F2207/3884
摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.
摘要翻译：乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。

19. 发明授权

US07565388B1 Logic cell supporting addition of three binary words 有权
标题翻译：逻辑单元支持添加三个二进制字
公开(公告)号：US07565388B1
公开(公告)日：2009-07-21
申请号：US10718968
申请日：2003-11-21
申请人： Gregg Baeckler , Martin Langhammer , James Schleicher , Richard Yuan
发明人： Gregg Baeckler , Martin Langhammer , James Schleicher , Richard Yuan
IPC分类号： G06F7/38 , G06F7/50
CPC分类号： G06F7/509 , H03K19/1733
摘要： Logic circuits that support the addition of three binary numbers using hardwired adders are described. In one embodiment, this is accomplished by using a 3:2 compressor (i.e., a Carry Save Adder method), using hardwired adders to add the sums and carrys produced by the 3:2 compression, and sharing carrys data calculated in one logic element (“LE”) with the following LE. In such an embodiment, with the exception of the first and last LEs in a logic array block (“LAB”), each LE in effect lends one look-up table (“LUT”) to the LE below (i.e., the following LE) and borrows one LUT from the LE above (i.e., the previous LE). The LUT being lent or borrowed is one that implements the carry function in the 3:2 compressor model. In another aspect, an embodiment of the present invention provides LEs that include selectors to select signals corresponding to the addition of three binary numbers mode.
摘要翻译：描述了支持使用硬连线加法器添加三个二进制数的逻辑电路。在一个实施例中，这是通过使用3：2压缩器（即，进位保存加法器方法）来实现的，其使用硬连线加法器来添加由3：2压缩产生的和和携带，并且共享携带在一个逻辑元件中计算的数据（“LE”）与以下LE。在这样的实施例中，除了逻辑阵列块（“LAB”）中的第一个和最后一个LE之外，每个LE有效地将一个查找表（“LUT”）提供给下面的LE（即，下面的LE ）并从上面的LE借用一个LUT（即，先前的LE）。借出或借用的LUT是在3：2压缩机模型中实现进位功能的LUT。在另一方面，本发明的实施例提供了包括选择器的LE，用于选择对应于三进制数模式的添加的信号。

20. 发明授权

US07467176B2 Saturation and rounding in multiply-accumulate blocks 有权
标题翻译：多重积累块中的饱和度和舍入
公开(公告)号：US07467176B2
公开(公告)日：2008-12-16
申请号：US10783829
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号： G06F7/38
CPC分类号： G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要： Saturation and rounding capabilities are implemented in multiply-accumulate (MAC) blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译：饱和度和舍入能力在乘法累加（MAC）块中实现，以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累加电路。这些功能支持任何合适的价值表示形式，包括x.15格式。乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。

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