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11. 发明申请

US20080294875A1 PARALLEL PROCESSOR FOR EFFICIENT PROCESSING OF MOBILE MULTIMEDIA 有权
标题翻译：并行处理器对移动多媒体的高效处理
公开(公告)号：US20080294875A1
公开(公告)日：2008-11-27
申请号：US12045844
申请日：2008-03-11
申请人： Chun Gi LYUH , Yil Suk YANG , Se Wan HEO , Soon Il YEO , Tae Moon ROH , Jong Dae KIM , Ki Chul KIM , Se Hoon YOO
发明人： Chun Gi LYUH , Yil Suk YANG , Se Wan HEO , Soon Il YEO , Tae Moon ROH , Jong Dae KIM , Ki Chul KIM , Se Hoon YOO
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F15/8007
摘要： Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.
摘要翻译：提供了一种用于支持浮点运算的并行处理器。并行处理器具有灵活的结构，便于开发涉及多媒体计算的并行算法，需要较低的硬件成本，并且消耗低功耗。为了支持浮点运算，并行处理器使用浮点累加器和浮点乘法的标志。使用并行处理器，可以以低成本在三维（3D）图形处理中处理几何变换操作。此外，可以通过分区单指令多数据（SIMD）方法和有条件执行指令的方法来最小化用于指令的总线宽度的成本。

12. 发明授权

US07391249B2 Multi-threshold CMOS latch circuit 失效
标题翻译：多阈值CMOS锁存电路
公开(公告)号：US07391249B2
公开(公告)日：2008-06-24
申请号：US11607743
申请日：2006-12-01
申请人： Dae Woo Lee , Yil Suk Yang , Gyu Hyun Kim , Soon Il Yeo , Jong Dae Kim
发明人： Dae Woo Lee , Yil Suk Yang , Gyu Hyun Kim , Soon Il Yeo , Jong Dae Kim
IPC分类号： H03K3/289
CPC分类号： H03K3/356156 , H03K3/012
摘要： Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.
摘要翻译：提供了一种多阈值互补金属氧化物半导体（MTCMOS）锁存电路，包括：数据反相电路，用于在睡眠控制信号的控制下反相输出输入数据; 传输门，用于在时钟控制信号的控制下传送从数据反相电路输出的数据信号; 信号控制电路，用于在复位控制信号和睡眠控制信号的控制下输出从传输门输出的数据信号; 以及用于反馈从信号控制电路输出的信号并且以睡眠模式保存数据的反馈电路。 MTCMOS锁存电路可以将由于按比例缩小到纳米级的元件引起的漏电流引起的功耗最小化，并且还通过使用具有低阈值电压的元件有助于逻辑电路的高速操作。

13. 发明申请

US20080140745A1 Arithmetic method and device of reconfigurable processor 失效
标题翻译：可重构处理器的算术方法和装置
公开(公告)号：US20080140745A1
公开(公告)日：2008-06-12
申请号：US11978878
申请日：2007-10-30
申请人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
发明人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
IPC分类号： G06F5/01
CPC分类号： G06F7/57
摘要： Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.
摘要翻译：提供了可重构处理器的算术方法和装置。算术装置包括：用于执行加法运算和减法运算的算术逻辑单元（ALU）和二进制信号的逻辑运算; 用于执行二进制信号的乘法运算的乘法器; 用于改变二进制信号的布置的移位器; 每个用于选择从所述ALU，所述乘法器和所述移位器输出的值之一的第一操作数选择器和第二操作数选择器; 以及用于将由第一操作数选择器和第二操作数选择器选择的值相加的加法器。

14. 发明授权

US08166328B2 Low power consumption processor 有权
标题翻译：低功耗处理器
公开(公告)号：US08166328B2
公开(公告)日：2012-04-24
申请号：US12427291
申请日：2009-04-21
申请人： Yil-Suk Yang , Tae-Moon Roh , Soon-Il Yeo , Jung-Hee Suk , Chun-Gi Lyuh , Ik-Jae Chun , Se-Wan Heo , Jong-Dae Kim
发明人： Yil-Suk Yang , Tae-Moon Roh , Soon-Il Yeo , Jung-Hee Suk , Chun-Gi Lyuh , Ik-Jae Chun , Se-Wan Heo , Jong-Dae Kim
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/3296 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： Provided is a low power consumption processor. The processor includes: a plurality of blocks; a memory storing instructions that control each of the plurality of blocks; and a multi power controller generates a signal that activates at least one of the plurality of blocks according to an address storing the instruction, and provides a normal power voltage or a reduction power voltage in response to the activation signal.
摘要翻译：提供了一种低功耗处理器。处理器包括：多个块; 存储器，其存储控制所述多个块中的每一个的指令; 并且多功率控制器根据存储该指令的地址产生激活多个块中的至少一个块的信号，并且响应于激活信号提供正常电力电压或降低功率电压。

15. 发明授权

US08643999B2 Electromagnetic interference reduction apparatus 失效
标题翻译：电磁干扰降低装置
公开(公告)号：US08643999B2
公开(公告)日：2014-02-04
申请号：US13211149
申请日：2011-08-16
申请人： Soon Il Yeo
发明人： Soon Il Yeo
IPC分类号： H02J7/00
CPC分类号： H05K9/0081 , H01L35/00
摘要： Provided is an Electromagnetic Interference (EMI) reduction apparatus. The EMI reduction apparatus includes: an electromagnetic wave absorbing unit absorbing electromagnetic waves from an electromagnetic wave generator and converting the absorbed electromagnetic waves into thermal energy through thermal conversion and emitting the thermal energy; and a thermoelectric unit converting the emitted thermal energy into electric energy.
摘要翻译：提供了一种电磁干扰（EMI）减小装置。 EMI降低装置包括：电磁波吸收单元，其吸收来自电磁波发生器的电磁波，并且通过热转换将吸收的电磁波转换成热能并发射热能; 以及将发射的热能转换为电能的热电单元。

16. 发明申请

US20100257342A1 ROW OF FLOATING POINT ACCUMULATORS COUPLED TO RESPECTIVE PES IN UPPERMOST ROW OF PE ARRAY FOR PERFORMING ADDITION OPERATION 审中-公开
标题翻译：浮动点累积器与适用于执行添加操作的PE阵列的更高层次的PES相关联的方法
公开(公告)号：US20100257342A1
公开(公告)日：2010-10-07
申请号：US12817407
申请日：2010-06-17
申请人： Chun Gi LYUH , Yil Suk YANG , Se Wan HEO , Soon Il YEO , Tae Moon ROH , Jong Dae KIM , Ki Chul KIM , Se Hoon YOO
发明人： Chun Gi LYUH , Yil Suk YANG , Se Wan HEO , Soon Il YEO , Tae Moon ROH , Jong Dae KIM , Ki Chul KIM , Se Hoon YOO
IPC分类号： G06F9/302
CPC分类号： G06F15/8007
摘要： Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.
摘要翻译：提供了一种用于支持浮点运算的并行处理器。并行处理器具有灵活的结构，便于开发涉及多媒体计算的并行算法，需要较低的硬件成本，并且消耗低功耗。为了支持浮点运算，并行处理器使用浮点累加器和浮点乘法的标志。使用并行处理器，可以以低成本在三维（3D）图形处理中处理几何变换操作。此外，可以通过分区单指令多数据（SIMD）方法和有条件执行指令的方法来最小化用于指令的总线宽度的成本。

17. 发明授权

US07793006B2 Method and apparatus for managing reconfiguration data memory with a preservation data storing buffer in the target system and server 失效
标题翻译：用于在目标系统和服务器中用保存数据存储缓冲器来管理重配置数据存储器的方法和装置
公开(公告)号：US07793006B2
公开(公告)日：2010-09-07
申请号：US10917727
申请日：2004-08-13
申请人： Soon Il Yeo , Myung Shin Kwak , Jong Dae Kim
发明人： Soon Il Yeo , Myung Shin Kwak , Jong Dae Kim
IPC分类号： G06F3/00 , G06F5/00 , G06F13/00 , G06F12/00 , G06F9/00 , G06F9/44
CPC分类号： H04L67/025
摘要： Provided are an apparatus and a method of managing a reconfiguration data memory. A space for a memory that stores configuration data used for reconfiguration of a target system is not provided in the target system. Instead the configuration data is stored in a separate server and, if required, the configuration data is transmitted to the target system through an Internet. Data that should be preserved after the reconfiguration among data contents stored in SoC internal and external memories of the target system is transferred to the server. The emptied space of the SoC internal and external memories is used as a configuration memory. After the reconfiguration, the preservation data is returned to its original position in the memories.
摘要翻译：提供了一种管理重配置数据存储器的装置和方法。用于存储用于重新配置目标系统的配置数据的存储器的空间不在目标系统中提供。而是将配置数据存储在单独的服务器中，如果需要，配置数据将通过Internet传输到目标系统。在存储在目标系统的SoC内部和外部存储器中的数据内容重新配置后应保留的数据将传输到服务器。 SoC内部和外部存储器的空的空间用作配置存储器。在重新配置之后，保存数据返回到其在存储器中的原始位置。

18. 发明授权

US08304895B2 Semiconductor package and method of fabricating the same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US08304895B2
公开(公告)日：2012-11-06
申请号：US12764330
申请日：2010-04-21
申请人： Woojin Chang , Soon Il Yeo , Hae Cheon Kim , Eun Soo Nam
发明人： Woojin Chang , Soon Il Yeo , Hae Cheon Kim , Eun Soo Nam
IPC分类号： H01L23/053
CPC分类号： H01L23/5389 , H01L23/3107 , H01L24/83 , H01L24/90 , H01L25/03 , H01L2224/90 , H01L2924/00011 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2224/83851 , H01L2924/00
摘要： A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal.
摘要翻译：提供半导体封装。半导体封装包括封装体，多个半导体芯片和外部连接端子。封装体与设置有导电图案和通孔的多个片层叠。多个半导体芯片被插入到从封装主体的一个表面延伸的插入槽中。外部连接端子设置在与封装主体的一个表面相对的另一表面上。这里，多个半导体芯片电连接到外部连接端子。

19. 发明申请

US20120161803A1 APPARATUS AND METHOD FOR NEAR FIELD SCAN CALIBRATION 失效
标题翻译：近场扫描校准的装置和方法
公开(公告)号：US20120161803A1
公开(公告)日：2012-06-28
申请号：US13323842
申请日：2011-12-13
申请人： SOON IL YEO , Jae Kyung Wee , Pil Soo Lee
发明人： SOON IL YEO , Jae Kyung Wee , Pil Soo Lee
IPC分类号： G01R35/00
CPC分类号： G01R35/00 , G01R29/0814 , G01R29/0892
摘要： Disclosed are a method and an apparatus of near field scan calibration, and more particularly, a method and an apparatus for near field scan calibration for calibrating a characteristic of an antenna for near field scan measurement of a semiconductor chip. The apparatus for near field scan calibration includes: a plane-type text fixture having a plane shape; an antenna positioned spaced apart from the plane-type test fixture by a set spacing distance and acquiring data including a magnetic field; and a spectrum analyzer analyzing the data acquired by the antenna.
摘要翻译：公开了近场扫描校准的方法和装置，更具体地，涉及用于校准半导体芯片的近场扫描测量的天线的特性的近场扫描校准的方法和装置。用于近场扫描校准的装置包括：具有平面形状的平面型文本夹具; 天线，其与平面型测试夹具间隔一定距离并获取包括磁场的数据; 以及分析由天线获取的数据的频谱分析仪。

20. 发明申请

US20070126486A1 Multi-threshold CMOS latch circuit 失效
标题翻译：多阈值CMOS锁存电路
公开(公告)号：US20070126486A1
公开(公告)日：2007-06-07
申请号：US11607743
申请日：2006-12-01
申请人： Dae Woo Lee , Yil Suk Yang , Gyu Hyun Kim , Soon Il Yeo , Jong Dae Kim
发明人： Dae Woo Lee , Yil Suk Yang , Gyu Hyun Kim , Soon Il Yeo , Jong Dae Kim
IPC分类号： H03K3/00
CPC分类号： H03K3/356156 , H03K3/012
摘要： Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.
摘要翻译：提供了一种多阈值互补金属氧化物半导体（MTCMOS）锁存电路，包括：数据反相电路，用于在睡眠控制信号的控制下反相输出输入数据; 传输门，用于在时钟控制信号的控制下传送从数据反相电路输出的数据信号; 信号控制电路，用于在复位控制信号和睡眠控制信号的控制下输出从传输门输出的数据信号; 以及用于反馈从信号控制电路输出的信号并且以睡眠模式保存数据的反馈电路。 MTCMOS锁存电路可以将由于按比例缩小到纳米级的元件引起的漏电流引起的功耗最小化，并且还通过使用具有低阈值电压的元件有助于逻辑电路的高速操作。

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