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1. 发明授权

US09031774B2 Apparatus and method for preventing collision of vehicle 有权
标题翻译：用于防止车辆碰撞的装置和方法
公开(公告)号：US09031774B2
公开(公告)日：2015-05-12
申请号：US12779221
申请日：2010-05-13
申请人： Jung Hee Suk , Ik Jae Chun , Chun Gi Lyuh , Soon Il Yeo , Wook Jin Chung , Jeong Hwan Lee , Jae Chang Shim , Tae Moon Roh
发明人： Jung Hee Suk , Ik Jae Chun , Chun Gi Lyuh , Soon Il Yeo , Wook Jin Chung , Jeong Hwan Lee , Jae Chang Shim , Tae Moon Roh
IPC分类号： G05D1/02 , B62D15/02 , B60W30/12 , B60W30/18 , G06K9/00 , G08G1/16
CPC分类号： B62D15/0265 , B60W30/12 , B60W30/18163 , G06K9/00798 , G06K9/00805 , G08G1/16 , G08G1/166 , G08G1/167 , Y02T10/84
摘要： The present invention provides an apparatus and method for predicting a moving direction of another vehicle running on a carriageway adjacent to a user's vehicle using periodically acquired image information around the user's vehicle, and performing a control process of preventing collision of the user's vehicle when a moving direction of the user's vehicle crosses the moving direction of the other vehicle.
摘要翻译：本发明提供一种用于使用周围获取的用户车辆周围的图像信息来预测在与车辆相邻的车道上行驶的另一车辆的移动方向的装置和方法，并且执行当移动时防止用户车辆的碰撞的控制处理使用者车辆的方向与另一车辆的移动方向相交。

2. 发明申请

US20120044664A1 ELECTROMAGNETIC INTERFERENCE REDUCTION APPARATUS 失效
标题翻译：电磁干扰减少装置
公开(公告)号：US20120044664A1
公开(公告)日：2012-02-23
申请号：US13211149
申请日：2011-08-16
申请人： Soon Il YEO
发明人： Soon Il YEO
IPC分类号： H05K9/00
CPC分类号： H05K9/0081 , H01L35/00
摘要： Provided is an Electromagnetic Interference (EMI) reduction apparatus. The EMI reduction apparatus includes: an electromagnetic wave absorbing unit absorbing electromagnetic waves from an electromagnetic wave generator and converting the absorbed electromagnetic waves into thermal energy through thermal conversion and emitting the thermal energy; and a thermoelectric unit converting the emitted thermal energy into electric energy.
摘要翻译：提供了一种电磁干扰（EMI）减小装置。 EMI降低装置包括：电磁波吸收单元，其吸收来自电磁波发生器的电磁波，并且通过热转换将吸收的电磁波转换成热能并发射热能; 以及将发射的热能转换为电能的热电单元。

3. 发明授权

US07769981B2 Row of floating point accumulators coupled to respective PEs in uppermost row of PE array for performing addition operation 有权
标题翻译：耦合到PE阵列的最上排中的相应PE的浮点累加器的行，用于执行附加操作
公开(公告)号：US07769981B2
公开(公告)日：2010-08-03
申请号：US12045844
申请日：2008-03-11
申请人： Chun Gi Lyuh , Yil Suk Yang , Se Wan Heo , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Se Hoon Yoo
发明人： Chun Gi Lyuh , Yil Suk Yang , Se Wan Heo , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Se Hoon Yoo
IPC分类号： G06F15/80
CPC分类号： G06F15/8007
摘要： Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.
摘要翻译：提供了一种用于支持浮点运算的并行处理器。并行处理器具有灵活的结构，便于开发涉及多媒体计算的并行算法，需要较低的硬件成本，并且消耗低功耗。为了支持浮点运算，并行处理器使用浮点累加器和浮点乘法的标志。使用并行处理器，可以以低成本在三维（3D）图形处理中处理几何变换操作。此外，可以通过分区单指令多数据（SIMD）方法和有条件执行指令的方法来最小化用于指令的总线宽度的成本。

4. 发明申请

US20070150763A1 Highly energy-efficient processor employing dynamic voltage scaling 有权
标题翻译：采用动态电压调节的高能效处理器
公开(公告)号：US20070150763A1
公开(公告)日：2007-06-28
申请号：US11520177
申请日：2006-09-13
申请人： Yil Suk Yang , Jong Dae Kim , Soon Il Yeo , Chun Gi Lyuh
发明人： Yil Suk Yang , Jong Dae Kim , Soon Il Yeo , Chun Gi Lyuh
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/3293 , G06F1/3296 , Y02D10/122 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： Provided is a highly energy-efficient processor architecture. The architecture employs 2-stage dynamic voltage scaling (DVS) and a sleep mode for high energy efficiency, dynamically controls the power supply voltage and activation of an embedded processor with instructions, and thus can prevent performance deterioration while reducing power consumption.A highly energy-efficient processor employing the processor architecture includes: a function unit block for performing an operation according to instructions input from the outside; at least one peripheral unit block for performing data communication with an external device; an instruction decoder for interpreting the input instructions and determining operation modes of the function unit block and peripheral unit block required for executing the interpreted instructions; a function unit block driver for applying a different power supply voltage according to the operation mode of the function unit block to the function unit block; and a peripheral unit block driver for applying a different power supply voltage according to the operation mode of the peripheral unit block to the peripheral unit block.
摘要翻译：提供了一种高能效的处理器架构。该架构采用2级动态电压调节（DVS）和睡眠模式以实现高能效，通过指令动态控制电源电压和嵌入式处理器的激活，从而可以在降低功耗的同时防止性能下降。采用该处理器架构的高能效处理器包括：功能单元块，用于根据从外部输入的指令进行操作; 用于与外部设备进行数据通信的至少一个外围单元块; 用于解释输入指令并确定执行解释指令所需的功能单元块和外围单元块的操作模式的指令解码器; 功能单元块驱动器，用于根据功能单元块的操作模式将不同的电源电压施加到功能单元块; 以及外围单元块驱动器，用于根据外围单元块的操作模式向外围单元块施加不同的电源电压。

5. 发明授权

US08786298B2 Apparatus and method for near field scan calibration 失效
标题翻译：用于近场扫描校准的装置和方法
公开(公告)号：US08786298B2
公开(公告)日：2014-07-22
申请号：US13323842
申请日：2011-12-13
申请人： Soon Il Yeo , Jae Kyung Wee , Pil Soo Lee
发明人： Soon Il Yeo , Jae Kyung Wee , Pil Soo Lee
IPC分类号： G01R31/00 , G01R35/00 , G01R29/08
CPC分类号： G01R35/00 , G01R29/0814 , G01R29/0892
摘要： Disclosed are a method and an apparatus of near field scan calibration, and more particularly, a method and an apparatus for near field scan calibration for calibrating a characteristic of an antenna for near field scan measurement of a semiconductor chip. The apparatus for near field scan calibration includes: a plane-type text fixture having a plane shape; an antenna positioned spaced apart from the plane-type test fixture by a set spacing distance and acquiring data including a magnetic field; and a spectrum analyzer analyzing the data acquired by the antenna.
摘要翻译：公开了近场扫描校准的方法和装置，更具体地，涉及用于校准半导体芯片的近场扫描测量的天线的特性的近场扫描校准的方法和装置。用于近场扫描校准的装置包括：具有平面形状的平面型文本夹具; 天线，其与平面型测试夹具间隔一定距离并获取包括磁场的数据; 以及分析由天线获取的数据的频谱分析仪。

6. 发明申请

US20110144859A1 APPARATUS AND METHOD FOR PREVENTING COLLISION OF VEHICLE 有权
标题翻译：防止车辆撞击的装置和方法
公开(公告)号：US20110144859A1
公开(公告)日：2011-06-16
申请号：US12779221
申请日：2010-05-13
申请人： Jung Hee SUK , Ik Jae CHUN , Chun Gi LYUH , Soon Il YEO , Wook Jin CHUNG , Jeong Hwan LEE , Jae Chang SHIM , Tae Moon ROH
发明人： Jung Hee SUK , Ik Jae CHUN , Chun Gi LYUH , Soon Il YEO , Wook Jin CHUNG , Jeong Hwan LEE , Jae Chang SHIM , Tae Moon ROH
IPC分类号： G08G1/16 , G06K9/00 , B62D6/00 , B60K31/00 , B62D15/02
CPC分类号： B62D15/0265 , B60W30/12 , B60W30/18163 , G06K9/00798 , G06K9/00805 , G08G1/16 , G08G1/166 , G08G1/167 , Y02T10/84
摘要： The present invention provides an apparatus and method for predicting a moving direction of another vehicle running on a carriageway adjacent to a user's vehicle using periodically acquired image information around the user's vehicle, and performing a control process of preventing collision of the user's vehicle when a moving direction of the user's vehicle crosses the moving direction of the other vehicle.
摘要翻译：本发明提供一种用于使用周围获取的用户车辆周围的图像信息来预测在与车辆相邻的车道上行驶的另一车辆的移动方向的装置和方法，并且执行当移动时防止用户车辆的碰撞的控制处理使用者车辆的方向与另一车辆的移动方向相交。

7. 发明授权

US07958179B2 Arithmetic method and device of reconfigurable processor 失效
标题翻译：可重构处理器的算术方法和装置
公开(公告)号：US07958179B2
公开(公告)日：2011-06-07
申请号：US11978878
申请日：2007-10-30
申请人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
发明人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
IPC分类号： G06F7/38
CPC分类号： G06F7/57
摘要： Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.
摘要翻译：提供了可重构处理器的算术方法和装置。算术装置包括：用于执行加法运算和减法运算的算术逻辑单元（ALU）和二进制信号的逻辑运算; 用于执行二进制信号的乘法运算的乘法器; 用于改变二进制信号的布置的移位器; 每个用于选择从ALU，乘法器和移位器输出的值之一的第一操作数选择器和第二操作数选择器; 以及用于将由第一操作数选择器和第二操作数选择器选择的值相加的加法器。

8. 发明授权

US07805620B2 Highly energy-efficient processor employing dynamic voltage scaling 有权
标题翻译：采用动态电压调节的高能效处理器
公开(公告)号：US07805620B2
公开(公告)日：2010-09-28
申请号：US11520177
申请日：2006-09-13
申请人： Yil Suk Yang , Jong Dae Kim , Soon Il Yeo , Chun Gi Lyuh
发明人： Yil Suk Yang , Jong Dae Kim , Soon Il Yeo , Chun Gi Lyuh
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/3293 , G06F1/3296 , Y02D10/122 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： Provided is a highly energy-efficient processor architecture. The architecture employs 2-stage dynamic voltage scaling (DVS) and a sleep mode for high energy efficiency, dynamically controls the power supply voltage and activation of an embedded processor with instructions, and thus can prevent performance deterioration while reducing power consumption.A highly energy-efficient processor employing the processor architecture includes: a function unit block for performing an operation according to instructions input from the outside; at least one peripheral unit block for performing data communication with an external device; an instruction decoder for interpreting the input instructions and determining operation modes of the function unit block and peripheral unit block required for executing the interpreted instructions; a function unit block driver for applying a different power supply voltage according to the operation mode of the function unit block to the function unit block; and a peripheral unit block driver for applying a different power supply voltage according to the operation mode of the peripheral unit block to the peripheral unit block.
摘要翻译：提供了一种高能效的处理器架构。该架构采用2级动态电压调节（DVS）和睡眠模式以实现高能效，通过指令动态控制电源电压和嵌入式处理器的激活，从而可以在降低功耗的同时防止性能下降。采用该处理器架构的高能效处理器包括：功能单元块，用于根据从外部输入的指令进行操作; 用于与外部设备进行数据通信的至少一个外围单元块; 用于解释输入指令并确定执行解释指令所需的功能单元块和外围单元块的操作模式的指令解码器; 功能单元块驱动器，用于根据功能单元块的操作模式将不同的电源电压施加到功能单元块; 以及外围单元块驱动器，用于根据外围单元块的操作模式向外围单元块施加不同的电源电压。

9. 发明申请

US20100162016A1 LOW POWER CONSUMPTION PROCESSOR 有权
标题翻译：低功耗处理器
公开(公告)号：US20100162016A1
公开(公告)日：2010-06-24
申请号：US12427291
申请日：2009-04-21
申请人： Yil-Suk YANG , Tae-Moon ROH , Soon-Il YEO , Jung-Hee SUK , Chun-Gi LYUH , Ik-Jae CHUN , Se-Wan HEO , Jong-Dae KIM
发明人： Yil-Suk YANG , Tae-Moon ROH , Soon-Il YEO , Jung-Hee SUK , Chun-Gi LYUH , Ik-Jae CHUN , Se-Wan HEO , Jong-Dae KIM
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/3296 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： Provided is a low power consumption processor. The processor includes: a plurality of blocks; a memory storing instructions that control each of the plurality of blocks; and a multi power controller generates a signal that activates at least one of the plurality of blocks according to an address storing the instruction, and provides a normal power voltage or a reduction power voltage in response to the activation signal.
摘要翻译：提供了一种低功耗处理器。处理器包括：多个块; 存储器，其存储控制所述多个块中的每一个的指令; 并且多功率控制器根据存储该指令的地址产生激活多个块中的至少一个块的信号，并响应于激活信号提供正常的电源电压或降低功率电压。

10. 发明授权

US07464275B2 Apparatus for sequentially enabling and disabling multiple powers 失效
标题翻译：用于顺序启用和禁用多个功率的装置
公开(公告)号：US07464275B2
公开(公告)日：2008-12-09
申请号：US11213059
申请日：2005-08-26
申请人： Tae Young Lim , Han Jin Cho , Soon Il Yeo , Ig Kyun Kim , Kyoung Seon Shin , Hee Bum Jung
发明人： Tae Young Lim , Han Jin Cho , Soon Il Yeo , Ig Kyun Kim , Kyoung Seon Shin , Hee Bum Jung
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： Provided is an apparatus for controlling multiple powers which is capable of turning on and off the multiple powers in their priorities for systems or components to be supplied with the multiple powers such as a liquid crystal display (LCD) module. In the apparatus for controlling multiple powers, an on-signal of high level is applied to an input terminal, and an output of a control signal generating unit is sequentially changed to a high level whenever a clock is applied to a clock signal input terminal by one period, so that outputs of the multiple powers are sequentially output. In addition, an off signal of low level is applied to the input terminal, and an output of the control signal generating unit is changed to a low level in a reversal order whenever a clock is applied to the clock signal input terminal by one period, so that outputs of the multiple powers are interrupted in the reversal order.
摘要翻译：本发明提供了一种用于控制多个功率的装置，其能够在要提供给诸如液晶显示器（LCD）模块的多个功率的系统或组件的优先级中打开和关闭多个功率。在用于控制多个功率的装置中，将高电平的接通信号施加到输入端，并且每当时钟被施加到时钟信号输入端时，控制信号产生单元的输出被顺序地改变为高电平一个周期，从而顺序输出多个功率的输出。此外，只要将时钟施加到时钟信号输入端子一个周期，则将低电平的关闭信号施加到输入端子，并且控制信号产生单元的输出以反转次序改变为低电平，使得多个功率的输出以反转顺序中断。

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