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11. 发明申请

US20120027026A1 SCALABLE INTERCONNECT MODULES WITH FLEXIBLE CHANNEL BONDING 有权
标题翻译：具有灵活通道连接的可扩展互连模块
公开(公告)号：US20120027026A1
公开(公告)日：2012-02-02
申请号：US12845672
申请日：2010-07-28
申请人： Keith Duwel , Michael Menghui Zheng , Vinson Chan , Kalyan Kankipati
发明人： Keith Duwel , Michael Menghui Zheng , Vinson Chan , Kalyan Kankipati
IPC分类号： H04J3/16
CPC分类号： H04J3/1682 , H04J3/04 , H04J3/0685 , H04L5/22 , H04Q2213/13208 , H04Q2213/13322
摘要： The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.
摘要翻译：本申请公开了用于增加集成电路（IC）的高速串行接口的信道利用的装置和方法。公开了一种新的电路架构，其提供可以被灵活地编程以支持多种不同的信道绑定方案的电路。根据本发明的一个方面，新架构使控制信号信道绑定的粒度与数据聚合信道绑定的粒度分离。这有利地允许优化用于两种类型的通道结合的配置。在本发明的另一方面，粘合用户信道的逻辑边界与PCS模块的物理边界分离。这种去耦有利地消除了先前架构的刚性约束。

12. 发明授权

US07343569B1 Apparatus and method for reset distribution 有权
标题翻译：复位分配的装置和方法
公开(公告)号：US07343569B1
公开(公告)日：2008-03-11
申请号：US11351425
申请日：2006-02-10
申请人： John Lam , Arch Zaliznyak , Chong Lee , Rakesh Patel , Vinson Chan
发明人： John Lam , Arch Zaliznyak , Chong Lee , Rakesh Patel , Vinson Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/66
摘要： A skew-tolerant, glitch-free reset distribution apparatus and method are provided in an intellectual property (IP) block that supports a multi-channel input/output protocol. During reset mode, synchronizers are used to create more predictable timing, to pipeline the propagation delay, and to tolerate RC-induced skews of up to a clock period in routing a reset signal to all the channels and within the channels in an IP block. Two control signals, which are available from programmable logic resource core circuitry, are used to control the input of the reset signal into the IP block. Because the control signals are designed to be glitch-free, the reset signal is therefore also glitch-free, thus preventing the IP block from inadvertently transitioning into or out of reset mode.
摘要翻译：在支持多通道输入/输出协议的知识产权（IP）块中提供了容错，无毛刺的复位分配装置和方法。在复位模式期间，使用同步器创建更可预测的时序，流水线传播延迟，并允许在将复位信号路由到IP模块中的所有通道和通道内的RC时钟周期的RC引起的偏差。两个控制信号可从可编程逻辑资源核心电路获得，用于控制复位信号输入到IP模块。由于控制信号被设计为无毛刺，因此复位信号也无毛刺，从而防止IP块无意中转换或复位。

13. 发明授权

US09531646B1 Multi-protocol configurable transceiver including configurable deskew in an integrated circuit 有权
标题翻译：多协议可配置收发器，包括集成电路中的可配置的偏移校正
公开(公告)号：US09531646B1
公开(公告)日：2016-12-27
申请号：US12632744
申请日：2009-12-07
申请人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee , Vinson Chan
发明人： Divya Vijayaraghavan , Curt Wortman , Chong H. Lee , Vinson Chan
IPC分类号： G06F3/00 , H04L12/861 , G06F5/10
CPC分类号： H04L49/90 , G06F5/10
摘要： Embodiments include a configurable multi-protocol transceiver including configurable deskew circuitry. In one embodiment, configurable circuitry is adapted to control an allowed data depth of a plurality of buffers. In another embodiment, configurable circuitry is adapted to control a deskew character transmit insertion frequency. In another embodiment, a programmable state machine is adapted to control read and write pointers in accordance with selectable conditions for achieving an alignment lock condition. In another embodiment, configurable circuitry is adaptable to select between logic and routing resources in the transceiver and logic and routing resources in a core of the IC in which the transceiver is implemented for controlling at least certain deskew operations. In another embodiment, configurable selection circuitry allows deskew processing to occur in a data path either before or after clock compensation processing depending on a communication protocol for which the transceiver is to be configured.
摘要翻译：实施例包括可配置的多协议收发器，包括可配置的偏移电路。在一个实施例中，可配置电路适于控制多个缓冲器的允许数据深度。在另一个实施例中，可配置电路适于控制偏斜字符传输插入频率。在另一个实施例中，可编程状态机适于根据用于实现对准锁定状态的可选条件来控制读取和写入指针。在另一个实施例中，可配置电路适于在收发器中的逻辑和路由资源之间选择逻辑，并且在IC的核心中布线资源，其中实现收发器用于控制至少某些去歪斜操作。在另一个实施例中，可配置的选择电路允许在时钟补偿处理之前或之后在数据路径中进行偏移处理，这取决于要配置收发器的通信协议。

14. 发明授权

US07724598B1 Megafunction block and interface 有权
标题翻译：宏功能块和接口
公开(公告)号：US07724598B1
公开(公告)日：2010-05-25
申请号：US11737654
申请日：2007-04-19
申请人： Vinson Chan , Chong H. Lee , Binh Ton , Thiagaraja Gopalsamy , Marcel A. LeBlanc , Neville Carvalho
发明人： Vinson Chan , Chong H. Lee , Binh Ton , Thiagaraja Gopalsamy , Marcel A. LeBlanc , Neville Carvalho
IPC分类号： G11C7/00
CPC分类号： G06F12/0292 , G06F12/0623 , G06F2212/1048
摘要： A megafunction block is provided that includes a serial interface enabling a user to specify settings of a configurable block of a programmable logic device. The megafunction block includes a register array having the capability of translating address information into actual addresses for a memory of the configurable block. Thus, as future configurations/standards are developed that a programmable logic device with the megafunction block will interfaces with, the settings for interfacing with the standards may be added to the register array. Consequently, the pin count will not need to increase as the megafunction block is scalable through the register map. Control logic verifies that the translated address is a valid address and the control logic will generate a selection signal based on whether a read or write operation is to be performed.
摘要翻译：提供了一种宏功能块，其包括使得用户能够指定可编程逻辑器件的可配置块的设置的串行接口。宏功能块包括具有将地址信息转换成可配置块的存储器的实际地址的能力的寄存器阵列。因此，随着具有宏功能块的可编程逻辑器件将与之相接的未来配置/标准被开发，用于与标准接口的设置可被添加到寄存器阵列中。因此，引脚数不需要增加，因为宏功能块可通过寄存器映射进行扩展。控制逻辑验证翻译的地址是否是有效地址，并且控制逻辑将基于是执行读操作还是写操作来生成选择信号。

15. 发明授权

US07071726B1 Selectable dynamic reconfiguration of programmable embedded IP 失效
标题翻译：可编程嵌入式IP的可选择动态重新配置
公开(公告)号：US07071726B1
公开(公告)日：2006-07-04
申请号：US11005390
申请日：2004-12-01
申请人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata , Binh Ton
发明人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata , Binh Ton
IPC分类号： H03K19/00
CPC分类号： H03K19/17752 , H03K19/17732 , H03K19/17736 , H03K19/17744
摘要： Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the invention may include at least two different signal paths between the PLD core fabric and embedded IP building blocks. Either one, or both, of these two paths may be used for configuration and/or implementation of the embedded IP building blocks.
摘要翻译：提供了PLD的核心PLD结构与驻留在其中的嵌入式IP构建块之间的改进的通信和改进的通信接口。根据本发明的电路可以包括PLD核心结构和嵌入式IP构建块之间的至少两个不同的信号路径。这两个路径中的一个或两者可以用于嵌入式IP构建块的配置和/或实现。

16. 发明授权

US07028270B1 Apparatus and method for reset distribution 失效
标题翻译：复位分配的装置和方法
公开(公告)号：US07028270B1
公开(公告)日：2006-04-11
申请号：US10621074
申请日：2003-07-15
申请人： John Lam , Arch Zaliznyak , Chong Lee , Rakesh Patel , Vinson Chan
发明人： John Lam , Arch Zaliznyak , Chong Lee , Rakesh Patel , Vinson Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/66
摘要： A skew-tolerant, glitch-free reset distribution apparatus and method are provided in an intellectual property (IP) block that supports a multi-channel input/output protocol. During reset mode, synchronizers are used to create more predictable timing, to pipeline the propagation delay, and to tolerate RC-induced skews of up to a clock period in routing a reset signal to all the channels and within the channels in an IP block. Two control signals, which are available from programmable logic resource core circuitry, are used to control the input of the reset signal into the IP block. Because the control signals are designed to be glitch-free, the reset signal is therefore also glitch-free, thus preventing the IP block from inadvertently transitioning into or out of reset mode.
摘要翻译：在支持多通道输入/输出协议的知识产权（IP）块中提供了容错，无毛刺的复位分配装置和方法。在复位模式期间，使用同步器创建更可预测的时序，流水线传播延迟，并允许在将复位信号路由到IP模块中的所有通道和通道内的RC时钟周期的RC引起的偏差。两个控制信号可从可编程逻辑资源核心电路获得，用于控制复位信号输入到IP模块。由于控制信号被设计为无毛刺，因此复位信号也无毛刺，从而防止IP块无意中转换或复位。

17. 发明授权

US06970117B1 Byte alignment for serial data receiver 失效
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US06970117B1
公开(公告)日：2005-11-29
申请号：US10789406
申请日：2004-02-26
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M9/00 , H04L7/02
CPC分类号： H04L7/0054 , H03M9/00
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

18. 发明授权

US06239615B1 High-performance interconnect 有权
标题翻译：高性能互连
公开(公告)号：US06239615B1
公开(公告)日：2001-05-29
申请号：US09235371
申请日：1999-01-20
申请人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
发明人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H01L23/5222 , H01L2924/0002 , H03K19/1778 , H03K19/17792 , H03K19/17796 , H01L2924/00
摘要： Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.
摘要翻译：为集成电路提供高性能互连的技术将提高整体集成电路性能。这些技术包括布置，布置和制造信号导体（例如，405,720），使得寄生耦合电容（例如425）最小化并且寄生电阻降低。这些技术将最小化导体之间串扰噪声的影响，从而提高整体集成电路性能。

19. 发明授权

US08488623B2 Scalable interconnect modules with flexible channel bonding 有权
公开(公告)号：US08488623B2
公开(公告)日：2013-07-16
申请号：US12845672
申请日：2010-07-28
申请人： Keith Duwel , Michael Menghui Zheng , Vinson Chan , Kalyan Kankipati
发明人： Keith Duwel , Michael Menghui Zheng , Vinson Chan , Kalyan Kankipati
IPC分类号： H04J3/16 , H04J3/22 , H04J3/06
CPC分类号： H04J3/1682 , H04J3/04 , H04J3/0685 , H04L5/22 , H04Q2213/13208 , H04Q2213/13322
摘要： The present application discloses apparatus and methods for increasing channel utilization for a high-speed serial interface of an integrated circuit (IC). A new circuit architecture is disclosed which provides circuitry that may be programmed flexibly to support a multitude of different channel bonding schemes. In accordance with one aspect of the invention, the new architecture decouples the granularity of control-signal channel bonding from the granularity of data-aggregation channel bonding. This advantageously allows optimization of configurations for both types of channel bonding. In another aspect of the invention, the logical boundaries of bonded user channels are decoupled from the physical boundaries of the PCS modules. This decoupling advantageously eliminates a rigid constraint of previous architectures.

20. 发明授权

US07362833B1 Dynamic special character selection for use in byte alignment circuitry 有权
标题翻译：用于字节对齐电路的动态特殊字符选择
公开(公告)号：US07362833B1
公开(公告)日：2008-04-22
申请号：US10609091
申请日：2003-06-27
申请人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata
发明人： Vinson Chan , Chong Lee , Rakesh Patel , Ramanand Venkata
IPC分类号： H04B1/10
CPC分类号： H04J3/0608
摘要： Circuitry for locating the boundaries of bytes in a data stream is provided. The data stream typically has comma or header information that provides an indication of the byte boundaries. When circuitry detects this information, it can align the byte boundaries and thereby provide byte-aligned data to utilization circuitry (e.g., a programmable logic device). In accordance with this invention, circuitry can select different special characters for use in detecting the byte boundaries, where the special characters are different lengths. Circuitry aligns the byte boundaries based on the selected special character when enabled by a control signal. Once aligned, circuitry can provide a signal indicating which special character was used to align the boundaries. Another advantage of the invention is that it eliminates alignment problems associated with system latency. Circuitry automatically locks alignment to a first instance of a detected special character independent of an external control signal.
摘要翻译：提供了用于定位数据流中字节边界的电路。数据流通常具有提供字节边界指示的逗号或头信息。当电路检测到该信息时，它可以对齐字节边界，从而向利用电路（例如，可编程逻辑器件）提供字节对齐的数据。根据本发明，电路可以选择用于检测字节边界的不同特殊字符，其中特殊字符是不同的长度。当控制信号使能时，电路会根据所选择的特殊字符对齐字节边界。一旦对准，电路可以提供一个信号，指示哪个特殊字符用于对齐边界。本发明的另一个优点是它消除了与系统延迟相关联的对准问题。电路自动将校准锁定到独立于外部控制信号的检测到的特殊字符的第一实例。

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