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1. 发明授权

US06281704B1 High-performance interconnect 有权
公开(公告)号：US06281704B1
公开(公告)日：2001-08-28
申请号：US09810116
申请日：2001-03-15
申请人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
发明人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
IPC分类号： H03K19177
摘要： Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.

2. 发明授权

US06239615B1 High-performance interconnect 有权
标题翻译：高性能互连
公开(公告)号：US06239615B1
公开(公告)日：2001-05-29
申请号：US09235371
申请日：1999-01-20
申请人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
发明人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H01L23/5222 , H01L2924/0002 , H03K19/1778 , H03K19/17792 , H03K19/17796 , H01L2924/00
摘要： Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.
摘要翻译：为集成电路提供高性能互连的技术将提高整体集成电路性能。这些技术包括布置，布置和制造信号导体（例如，405,720），使得寄生耦合电容（例如425）最小化并且寄生电阻降低。这些技术将最小化导体之间串扰噪声的影响，从而提高整体集成电路性能。

3. 发明授权

US6154059A High performance output buffer 有权
标题翻译：高性能输出缓冲器
公开(公告)号：US6154059A
公开(公告)日：2000-11-28
申请号：US199705
申请日：1998-11-24
申请人： Sammy Cheung , John Lam , Rakesh Patel , Tony Ngai
发明人： Sammy Cheung , John Lam , Rakesh Patel , Tony Ngai
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/00361
摘要： An output buffer has internal circuitry connected between an input node and an output node. The internal circuitry includes a quiet voltage supply connected to a first set of transistors of the internal circuitry and a noisy voltage supply connected to a second set of transistors of the internal circuitry. The noisy voltage supply is at a voltage level higher than the quiet voltage supply. The first set of transistors and the second set of transistors provide isolation between the noisy voltage supply and the quiet voltage supply. The first set of transistors and the second set of transistors also provide complete digital high and low internal signal levels by using at least one transistor operative to supplement the complete shut-off and turn-on of transistors of the first set of transistors and the second set of transistors. The output buffer also features a ground bounce circuit, a slew rate control circuit, a transition accelerator circuit, a Personal Computer Interface (PCI) compatibility circuit, and a PCI control circuit.
摘要翻译：输出缓冲器具有连接在输入节点和输出节点之间的内部电路。内部电路包括连接到内部电路的第一组晶体管的静音电压源和连接到内部电路的第二组晶体管的噪声电压源。嘈杂的电源电压处于高于静态电源的电压电平。第一组晶体管和第二组晶体管提供噪声电压源和安静电源之间的隔离。第一组晶体管和第二组晶体管还通过使用至少一个晶体管提供完整的数字高和低内部信号电平，该晶体管可操作地补充第一组晶体管的晶体管的完全截止和导通，第二组晶体管的第二组一组晶体管。输出缓冲器还具有接地反弹电路，压摆率控制电路，转换加速器电路，个人计算机接口（PCI）兼容性电路和PCI控制电路。

4. 发明授权

US08291355B2 Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
标题翻译：专用集成电路等效的可编程逻辑和相关方法
公开(公告)号：US08291355B2
公开(公告)日：2012-10-16
申请号：US12967851
申请日：2010-12-14
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： G06F17/50
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（HLE）的ASIC架构，提供FPGA等效FPGA以提供更高效和经济性，每个ASIC架构可以提供FPGA逻辑元件（LE）的全部功能的一部分）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

5. 发明申请

US20070210827A1 Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
标题翻译：专用集成电路等效的可编程逻辑和相关方法
公开(公告)号：US20070210827A1
公开(公告)日：2007-09-13
申请号：US11801082
申请日：2007-05-07
申请人： Kar Chua , Sammy Cheung , Hee Phoon , Kim Tan , Wei Goay
发明人： Kar Chua , Sammy Cheung , Hee Phoon , Kim Tan , Wei Goay
IPC分类号： H03K19/173
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分（“LE”）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

6. 发明授权

US06599764B1 Isolation testing scheme for multi-die packages 失效
标题翻译：多芯片封装的隔离测试方案
公开(公告)号：US06599764B1
公开(公告)日：2003-07-29
申请号：US09870354
申请日：2001-05-30
申请人： Boon Jin Ang , Sammy Cheung , Kar Keng Chua
发明人： Boon Jin Ang , Sammy Cheung , Kar Keng Chua
IPC分类号： H01L2166
CPC分类号： G01R31/2886 , H01L2224/05554 , H01L2224/48091 , H01L2224/48145 , H01L2924/00014 , H01L2924/00012
摘要： A test platform is configured to test a mult-die package having at a first die and a second die. The test platform includes a first lead that is connected to the VCC input on the first die. The test platform also includes a second lead that is connected to VCCIO input on the second die. The VCC input on the second die is connected to ground. The I/O pin of the second die can then be tri-stated using a control circuit disposed between the pre-driver and the driver of the I/O buffer.
摘要翻译：测试平台被配置为测试具有在第一管芯和第二管芯处的多管芯封装。测试平台包括一个第一引线，连接到第一个管芯上的VCC输入端。测试平台还包括连接到第二个芯片上的VCCIO输入的第二引脚。第二个管芯上的VCC输入端接地。然后可以使用设置在I / O缓冲器的预驱动器和驱动器之间的控制电路来将第二管芯的I / O引脚三态化。

7. 发明授权

US08504963B2 Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
标题翻译：专用集成电路等效的可编程逻辑和相关方法
公开(公告)号：US08504963B2
公开(公告)日：2013-08-06
申请号：US13614819
申请日：2012-09-13
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： G06F17/50
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分（“LE”）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

8. 发明申请

US20060001444A1 Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
标题翻译：专用集成电路等效的可编程逻辑和相关方法
公开(公告)号：US20060001444A1
公开(公告)日：2006-01-05
申请号：US10884460
申请日：2004-07-02
申请人： Kar Chua , Sammy Cheung , Hee Phoon , Kim Tan , Wei Goay
发明人： Kar Chua , Sammy Cheung , Hee Phoon , Kim Tan , Wei Goay
IPC分类号： G06F7/38 , H03K19/173 , G06F17/50
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分（“LE”）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

9. 发明申请

US20130002295A1 APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS 有权
标题翻译：可编程逻辑及相关方法的应用特定集成电路等效
公开(公告)号：US20130002295A1
公开(公告)日：2013-01-03
申请号：US13614819
申请日：2012-09-13
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： H03K19/173
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（HLE）的ASIC架构，提供FPGA等效FPGA以提供更高效和经济性，每个ASIC架构可以提供FPGA逻辑元件（LE）的全部功能的一部分）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

10. 发明申请

US20110084727A1 APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS 有权
标题翻译：可编程逻辑及相关方法的应用特定集成电路等效
公开(公告)号：US20110084727A1
公开(公告)日：2011-04-14
申请号：US12967851
申请日：2010-12-14
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分（“LE”）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

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