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21. 发明授权

US07934036B2 Interrupt-related circuits, systems, and processes 有权
标题翻译：中断相关电路，系统和过程
公开(公告)号：US07934036B2
公开(公告)日：2011-04-26
申请号：US12100534
申请日：2008-04-10
申请人： Gregory Conti , Franck Dahan
发明人： Gregory Conti , Franck Dahan
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： An electronic interrupt circuit includes an interrupt-related input line, a security-related status input line, a context-related status input line, and a conversion circuit having plural interrupt-related output lines and selectively operable in response to an interrupt-related signal on said interrupt-related input line depending on an active or inactive status of each of said security-related status input line and said context-related status input line.
摘要翻译：电子中断电路包括中断相关输入线，安全相关状态输入线，上下文相关状态输入线和具有多个中断相关输出线的转换电路，并且可响应于中断相关信号选择性地工作在所述中断相关输入线上，取决于所述安全相关状态输入线和所述上下文相关状态输入线中的每一个的活动状态或不活动状态。

22. 发明授权

US07890753B2 Secure mode for processors supporting MMU and interrupts 有权
标题翻译：支持MMU和中断的处理器的安全模式
公开(公告)号：US07890753B2
公开(公告)日：2011-02-15
申请号：US10256642
申请日：2002-09-27
申请人： Franck Dahan , Christian Roussel , Alain Chateau , Peter Cumming
发明人： Franck Dahan , Christian Roussel , Alain Chateau , Peter Cumming
IPC分类号： H04L29/06
CPC分类号： G06F21/556 , G06F9/30047 , G06F9/3802 , G06F9/468 , G06F12/1491 , G06F21/51 , G06F21/52 , G06F21/74 , G06F21/82 , G06F2221/2101 , G06F2221/2105 , G06F2221/2141 , G06F2221/2143 , G06F2221/2149 , G06F2221/2153
摘要： A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled. The structure of the activation sequence code accounts for caches, write buffer and MMU being enabled. The structure of the exit sequences code accounts for caches, write buffer and MMU being enabled. A specific way is provided to manage a safe exit of secure mode under generic interruptions and allows return from interruption through entry point and activation sequence and a proper resuming of the secure execution. A specific way is provided to manage the MMU in secure mode and provide data exchange between secure and non-secure environment.
摘要翻译：在包括处理器核心，指令和数据高速缓存，写入缓冲器和存储器管理单元的处理器系统上，数字系统被提供有以非侵入式方式内置的安全模式（第三级特权）。因此，在唯一可信软件是存储在ROM中的代码的平台上提供安全执行模式。特别是操作系统不受信任，所有本地应用程序都不被信任。提供了一种安全执行模式，当启用存储器管理单元（MMU）时允许虚拟寻址。安全执行模式允许指令和数据高速缓存启用。提供了一种安全执行模式，允许所有系统中断被隐藏。通过唯一的入口点输入安全模式。安全执行模式可以通过进入/退出条件的完整硬件评估来动态输入和退出。监视一个特定的条目条目，这些条目占用缓存，写入缓冲区和MMU被启用。激活序列代码的结构用于缓存，写入缓冲区和MMU被使能。退出序列代码的结构用于缓存，写入缓冲区和MMU被启用。提供了一种具体的方法来管理通用中断下安全模式的安全退出，并允许从中断通过入口点和激活顺序返回，并适当恢复安全执行。提供了以安全模式管理MMU的特定方式，并在安全和非安全环境之间提供数据交换。

23. 发明授权

US07840827B2 Display power management 有权
标题翻译：显示电源管理
公开(公告)号：US07840827B2
公开(公告)日：2010-11-23
申请号：US11559386
申请日：2006-11-13
申请人： Franck Dahan , Franck Seigneret , Gilles Dubost , Jean Noel
发明人： Franck Dahan , Franck Seigneret , Gilles Dubost , Jean Noel
IPC分类号： G06F1/32
CPC分类号： G09G5/363 , G09G5/18 , G09G5/39 , G09G2330/021
摘要： An apparatus and method for power management of a display system. A display controller couples to a memory storage device. A frame buffer in the memory storage device is filled with frames of information for display on a display device. The frames of information transfer to a display buffer in the display controller. The display controller transmits the frames of information from the display buffer to the display device. When frame information is not being transferred to the display controller, the display controller and the memory storage device may separately enter a power saving state. In power saving state, the display controller may continue to transmit frame information to the display device; however, power and a clock signal to components of display controller may be limited. When the display buffer is almost empty, the display controller exits power saving state to fill the display buffer.
摘要翻译：一种用于显示系统的电源管理的装置和方法。显示控制器耦合到存储器存储设备。存储器存储设备中的帧缓冲器被填充有用于在显示设备上显示的信息帧。信息帧传送到显示控制器中的显示缓冲器。显示控制器将信息帧从显示缓冲器发送到显示装置。当帧信息未被传送到显示控制器时，显示控制器和存储器存储设备可以分别进入省电状态。在省电状态下，显示控制器可以继续向显示装置发送帧信息; 然而，对显示控制器的组件的功率和时钟信号可能受到限制。当显示缓冲区几乎为空时，显示控制器退出省电状态以填充显示缓冲区。

24. 发明授权

US07587525B2 Power control with standby, wait, idle, and wakeup signals 有权
标题翻译：具有待机，等待，空闲和唤醒信号的电源控制
公开(公告)号：US07587525B2
公开(公告)日：2009-09-08
申请号：US11383416
申请日：2006-05-15
申请人： Franck Dahan , Franck Seigneret , Gilles Dubost
发明人： Franck Dahan , Franck Seigneret , Gilles Dubost
IPC分类号： G06F13/28 , G06F1/26
CPC分类号： G06F1/3228 , G06F1/3215 , G06F1/3237 , G06F1/324 , G06F1/325 , G06F1/3275 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： An apparatus and method for conserving power in a memory information transfer system. The system may include a direct memory access (DMA) controller coupled to a memory storage device and a peripheral device. The DMA controller transfers information from the memory storage device to a buffer in the peripheral device. The DMA controller may also transfer information from the buffer in the peripheral device to the memory storage device. When the peripheral device buffer does not have to be filled or emptied by the DMA controller, the DMA controller enters a standby mode. When the peripheral device buffer is full or empty, the DMA controller exits standby mode, empties or fills the peripheral device buffer, and reenters standby mode.
摘要翻译：一种用于在存储器信息传送系统中节省功率的装置和方法。该系统可以包括耦合到存储器存储设备和外围设备的直接存储器访问（DMA）控制器。 DMA控制器将信息从存储器存储设备传送到外围设备中的缓冲器。 DMA控制器还可以将信息从外围设备中的缓冲器传送到存储器存储设备。当外部设备缓冲区不需要由DMA控制器填充或清空时，DMA控制器进入待机模式。当外围设备缓冲区已满或空时，DMA控制器退出待机模式，清空或填充外围设备缓冲区，并重新进入待机模式。

25. 发明授权

US07237081B2 Secure mode for processors supporting interrupts 有权
标题翻译：支持中断的处理器的安全模式
公开(公告)号：US07237081B2
公开(公告)日：2007-06-26
申请号：US10256523
申请日：2002-09-27
申请人： Franck Dahan , Christian Roussel , Alain Chateau , Peter Cumming
发明人： Franck Dahan , Christian Roussel , Alain Chateau , Peter Cumming
IPC分类号： G06F12/14 , G06F11/30 , G06F12/00 , H04L9/32 , H04L9/00
CPC分类号： G06F21/556 , G06F9/30047 , G06F9/3802 , G06F9/468 , G06F12/1491 , G06F21/51 , G06F21/52 , G06F21/74 , G06F21/82 , G06F2221/2101 , G06F2221/2105 , G06F2221/2141 , G06F2221/2143 , G06F2221/2149 , G06F2221/2153
摘要： A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled. The structure of the activation sequence code accounts for caches, write buffer and MMU being enabled. The structure of the exit sequences code accounts for caches, write buffer and MMU being enabled. A specific way is provided to manage a safe exit of secure mode under generic interruptions and allows return from interruption through entry point and activation sequence and a proper resuming of the secure execution. A specific way is provided to manage the MMU in secure mode and provide data exchange between secure and non-secure environment.
摘要翻译：在包括处理器核心，指令和数据高速缓冲存储器，写入缓冲器和写入缓冲器的处理器系统中，数字系统被提供有以非侵入式方式构建的安全模式（3级的特权级别）内存管理单元。因此，在唯一可信软件是存储在ROM中的代码的平台上提供安全执行模式。特别是操作系统不受信任，所有本地应用程序都不被信任。提供了一种安全执行模式，当启用存储器管理单元（MMU）时允许虚拟寻址。安全执行模式允许指令和数据高速缓存启用。提供了一种安全执行模式，允许所有系统中断被隐藏。通过唯一的入口点输入安全模式。安全执行模式可以通过进入/退出条件的完整硬件评估来动态输入和退出。监视一个特定的条目条目，这些条目占用缓存，写入缓冲区和MMU被启用。激活序列代码的结构用于缓存，写入缓冲区和MMU被使能。退出序列代码的结构用于缓存，写入缓冲区和MMU被启用。提供了一种具体的方法来管理通用中断下安全模式的安全退出，并允许从中断通过入口点和激活顺序返回，并适当恢复安全执行。提供了以安全模式管理MMU的特定方式，并在安全和非安全环境之间提供数据交换。

26. 发明申请

US20070109292A1 Display Power Management 有权
标题翻译：显示电源管理
公开(公告)号：US20070109292A1
公开(公告)日：2007-05-17
申请号：US11559386
申请日：2006-11-13
申请人： Franck Dahan , Franck Seigneret , Gilles Dubost , Jean Noel
发明人： Franck Dahan , Franck Seigneret , Gilles Dubost , Jean Noel
IPC分类号： G09G5/00
CPC分类号： G09G5/363 , G09G5/18 , G09G5/39 , G09G2330/021
摘要： An apparatus and method for power management of a display system. A display controller couples to a memory storage device. A frame buffer in the memory storage device is filled with frames of information for display on a display device. The frames of information transfer to a display buffer in the display controller. The display controller transmits the frames of information from the display buffer to the display device. When frame information is not being transferred to the display controller, the display controller and the memory storage device may separately enter a power saving state. In power saving state, the display controller may continue to transmit frame information to the display device; however, power and a clock signal to components of display controller may be limited. When the display buffer is almost empty, the display controller exits power saving state to fill the display buffer.
摘要翻译：一种用于显示系统的电源管理的装置和方法。显示控制器耦合到存储器存储设备。存储器存储设备中的帧缓冲器被填充有用于在显示设备上显示的信息帧。信息帧传送到显示控制器中的显示缓冲器。显示控制器将信息帧从显示缓冲器发送到显示装置。当帧信息未被传送到显示控制器时，显示控制器和存储器存储设备可以分别进入省电状态。在省电状态下，显示控制器可以继续向显示装置发送帧信息; 然而，对显示控制器的组件的功率和时钟信号可能受到限制。当显示缓冲区几乎为空时，显示控制器退出省电状态以填充显示缓冲区。

27. 发明授权

US06989702B2 Retention register with normal functionality independent of retention power supply 有权
标题翻译：保持寄存器具有正常功能，独立于保持电源
公开(公告)号：US06989702B2
公开(公告)日：2006-01-24
申请号：US10613271
申请日：2003-07-03
申请人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh T. Mair , Peter H. Cumming , Franck Dahan
发明人： Uming Ko , David B. Scott , Sumanth Gururajarao , Hugh T. Mair , Peter H. Cumming , Franck Dahan
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356008 , G11C14/00
摘要： State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1–M3; M1–M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to anode (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality. In addition, an isolation apparatus is provided to retain an output of a logic module while the logic module is powered-down.
摘要翻译：提供了用于数字IC操作的低功率待机模式的状态保持寄存器，其中：差分电路（M 1 -M 3; M 1 -M 4）用于从常规功能锁存器加载阴影锁存器; 用于将数据从阴影锁存器恢复到正常功能锁存器的信号（REST，RESTZ）是“无关”信号，而阴影锁存器在低功耗待机模式期间保留数据; 来自阴影锁存器的保留数据经由连接到提供保留数据的阴影锁存器的阳极（N10）的晶体管栅极恢复到正常功能锁存器; 除了阴影锁存器电源（VRETAIN）之外的电源（VDD）为数据恢复操作供电; 并且正常功能锁存器可独立于高V 1晶体管（M 1，M 2，M 5和M 6; M 3，M 4，M 5和M 6）的工作状态工作，用于实现状态保留功能。此外，提供隔离装置以在逻辑模块断电时保持逻辑模块的输出。

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