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21. 发明申请

US20100202186A1 SEMICONDUCTOR MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF SCREENING THE SAME 有权
标题翻译：半导体存储器件，其制造方法及其筛选方法
公开(公告)号：US20100202186A1
公开(公告)日：2010-08-12
申请号：US12705010
申请日：2010-02-12
申请人： Mitsuru SATO , Masanori Komura , Hiroshi Kanno , Kenichi Murooka
发明人： Mitsuru SATO , Masanori Komura , Hiroshi Kanno , Kenichi Murooka
IPC分类号： G11C11/00 , G11C29/00 , H01L45/00 , H01L21/20
CPC分类号： H01L27/1021 , G11C29/832 , G11C29/88 , G11C2213/72 , H01L27/24 , H01L29/0657 , H01L29/868
摘要： A semiconductor memory device includes first and second memory cells each including a variable resistance element and a diode and having a pillar shape, and an insulating layer provided between the first memory cell and the second memory cell and including a void. A central portion of the diode has a smaller width than widths of upper and lower portions of the diode.
摘要翻译：半导体存储器件包括第一和第二存储器单元，每个存储器单元包括可变电阻元件和二极管，并具有柱形形状;以及绝缘层，设置在第一存储单元和第二存储单元之间并且包括空隙。二极管的中心部分的宽度比二极管的上部和下部的宽度小。

22. 发明申请

US20090068765A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法和制造半导体器件的装置
公开(公告)号：US20090068765A1
公开(公告)日：2009-03-12
申请号：US11969564
申请日：2008-01-04
申请人： Kenichi MUROOKA
发明人： Kenichi MUROOKA
IPC分类号： H01L21/02 , B32B37/14
CPC分类号： G03F9/703 , B82Y10/00 , B82Y40/00 , G03F7/0002 , G03F7/703 , G03F7/7035 , G03F9/7003 , G03F9/7038 , G03F9/7042 , H01L27/1469
摘要： A method of manufacturing a semiconductor device includes performing positioning between a transfer position of a pattern forming surface of a transfer original plate on which a pattern to be transferred is formed and a transferred position of a transferred surface of a transferred substrate to which the pattern is to be transferred; contacting the pattern forming surface with the transferred surface; and partly correcting the positional deviation between the transfer position of the pattern forming surface and the transferred position of the transferred surface in the in-plane direction, after the positioning is performed.
摘要翻译：一种制造半导体器件的方法包括：在其上形成有转印图案的转印原版的图案形成表面的转印位置与转印的基板的转印表面的转印位置之间进行定位，被转让使图案形成表面与转印表面接触; 并且在进行定位之后部分地校正图案形成表面的转印位置和转印表面在面内方向上的转印位置之间的位置偏差。

23. 发明申请

US20070285973A1 STORAGE DEVICE 失效
标题翻译：储存设备
公开(公告)号：US20070285973A1
公开(公告)日：2007-12-13
申请号：US11837097
申请日：2007-08-10
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： G11C23/00 , G11C2213/71 , G11C2213/77
摘要： The present invention provides a storage device including a first electrode, a plurality of second electrodes arranged opposite the first electrode across a gap, and a particle which is selectively placed in one of the gaps between the first electrode and the second electrodes and which is movable between the first electrode and the second electrode and between the adjacent second electrodes. A stored state is determined utilizing the presence of the particle.
摘要翻译：本发明提供了一种存储装置，其包括第一电极，跨越间隙与第一电极相对布置的多个第二电极和选择性地放置在第一电极和第二电极之间的间隙之一中并且可移动的在第一电极和第二电极之间以及相邻的第二电极之间。使用颗粒的存在来确定存储状态。

24. 发明授权

US08760908B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08760908B2
公开(公告)日：2014-06-24
申请号：US13235431
申请日：2011-09-18
申请人： Tetsuji Kunitake , Kenichi Murooka
发明人： Tetsuji Kunitake , Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C8/08 , G11C8/14 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0069 , G11C2013/0076 , G11C2213/71
摘要： A nonvolatile semiconductor memory device includes: a memory cell array which has a plurality of first lines, a plurality of second lines intersecting the plurality of first lines and a plurality of memory cells which store an electrically rewritable resistance value as data in a non-volatile manner; a first decoder which is connected to one ends of the plurality of first lines and selects the first lines; a second decoder which is connected to the plurality of second lines and selects the second lines; and a voltage applying circuit which is connected to one of the first and second decoders and which applies a predetermined voltage between the first and second lines selected by the first and second decoders. The second decoder sequentially selects the second lines in a direction from the other ends to the one ends of the first lines.
摘要翻译：非易失性半导体存储器件包括：存储单元阵列，其具有多个第一线，与多条第一线相交的多条第二线，以及存储电可重写电阻值作为非易失性数据的多个存储单元方式; 第一解码器，其连接到所述多个第一线的一端并选择所述第一线; 第二解码器，连接到所述多个第二线并选择所述第二线; 以及电压施加电路，其连接到第一和第二解码器中的一个，并且在由第一和第二解码器选择的第一和第二线之间施加预定电压。第二解码器从第一行的另一端到一端的方向依次选择第二行。

25. 发明授权

US08570786B2 Memory device and fabricating method thereof 有权
公开(公告)号：US08570786B2
公开(公告)日：2013-10-29
申请号：US13177857
申请日：2011-07-07
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： H01L45/122 , G11C13/0002 , G11C2213/71 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/124 , H01L45/146 , H01L45/147 , H01L45/1691
摘要： According to one embodiment, a memory device includes first interconnects, second interconnects, and a first memory cell. The first memory cell is located in an intersection of one of the first interconnects and one of the second interconnects. The first memory cell includes a first multilayer structure and a first variable resistance layer, the first multilayer structure including a first electrode, a first selector, and a first insulator which are stacked. The first selector and the first variable resistance layer are electrically connected in series between the one of the first interconnect and the one of the second interconnect. The first variable resistance layer is formed on a portion of a side surface of the first insulator to cover the portion without covering a residual portion.

26. 发明申请

US20130010520A1 MEMORY DEVICE AND FABRICATING METHOD THEREOF 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20130010520A1
公开(公告)日：2013-01-10
申请号：US13177857
申请日：2011-07-07
申请人： Kenichi MUROOKA
发明人： Kenichi MUROOKA
IPC分类号： G11C11/21 , H01L45/00 , H01L21/8239
CPC分类号： H01L45/122 , G11C13/0002 , G11C2213/71 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/124 , H01L45/146 , H01L45/147 , H01L45/1691
摘要： According to one embodiment, a memory device includes first interconnects, second interconnects, and a first memory cell. The first memory cell is located in an intersection of one of the first interconnects and one of the second interconnects. The first memory cell includes a first multilayer structure and a first variable resistance layer, the first multilayer structure including a first electrode, a first selector, and a first insulator which are stacked. The first selector and the first variable resistance layer are electrically connected in series between the one of the first interconnect and the one of the second interconnect. The first variable resistance layer is formed on a portion of a side surface of the first insulator to cover the portion without covering a residual portion.
摘要翻译：根据一个实施例，存储器件包括第一互连，第二互连和第一存储单元。第一存储器单元位于第一互连中的一个和第二互连中的一个的交叉点中。第一存储单元包括第一多层结构和第一可变电阻层，第一多层结构包括堆叠的第一电极，第一选择器和第一绝缘体。第一选择器和第一可变电阻层串联地电连接在第一互连和第二互连中的一个之间。第一可变电阻层形成在第一绝缘体的侧表面的一部分上以覆盖该部分而不覆盖剩余部分。

27. 发明授权

US08295077B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08295077B2
公开(公告)日：2012-10-23
申请号：US13001147
申请日：2009-06-11
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/0023 , G11C13/004 , G11C2013/0054 , G11C2213/71 , H01L27/115 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/085 , H01L45/10 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1675
摘要： A semiconductor memory device comprises a plurality of first row lines arranged in parallel; a plurality of column lines intersecting the first row lines; a plurality of storage elements arranged at intersections of the first row lines and the column lines; a plurality of second row lines arranged in parallel with the first row lines, from positions opposite to the first row lines via the column lines to a certain portion of the column line, and capacitively coupled with the column lines; and a sense amplifier including a field effect transistor having a lower layer control electrode composed of the certain portion of the column line, and an upper layer control electrode composed of the second row line capacitively coupled in the upper layer with the certain portion of the column line.
摘要翻译：半导体存储器件包括并行布置的多个第一行线; 与第一行线相交的多个列线; 多个存储元件，布置在第一行线和列线的交点处; 多条第二行线，与第一行线平行排列，从与第一列行相对的位置经由列线排列到列线的某一部分，并与列线电容耦合; 以及包括具有由列线的特定部分组成的下层控制电极的场效应晶体管的读出放大器，以及由上层的电容耦合到列的一定部分的第二行线构成的上层控制电极线。

28. 发明授权

US08086107B2 Optical-electrical hybrid integrated circuit 有权
标题翻译：光电混合集成电路
公开(公告)号：US08086107B2
公开(公告)日：2011-12-27
申请号：US12033330
申请日：2008-02-19
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： H04B10/00
CPC分类号： H04B10/801 , G02B6/43
摘要： An operating unit performs a prescribed operation and includes a standby-state-signal generating unit that generates a standby state signal for switching between a standby state and an operation state of the operating unit in a first part of the operating unit. An optical-signal transmitting unit converts an electric signal, which is a result of the operation in a second part of the operating unit, into an optical signal, transmits the optical signal to a third part of the operating unit, and then converts the optical signal into the electric signal. A power-supply control unit controls a supply of the electric power to the operating unit and a supply of the electric power to the optical-signal transmitting unit by a power supply unit in response to the standby state signal.
摘要翻译：操作单元执行规定的操作，并且包括在操作单元的第一部分中产生用于在待机状态和操作单元的操作状态之间切换的待机状态信号的待机状态信号生成单元。光信号发送单元将作为操作单元的第二部分的操作结果的电信号转换为光信号，将光信号发送到操作单元的第三部分，然后将光信号信号进入电信号。电源控制单元控制对操作单元的电力供应，并且响应于待机状态信号，通过电源单元向光信号发送单元供应电力。

29. 发明申请

US20110103128A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110103128A1
公开(公告)日：2011-05-05
申请号：US12882685
申请日：2010-09-15
申请人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue
发明人： Hiroshi Kanno , Reika Ichihara , Takayuki Tsukamoto , Kenichi Murooka , Hirofumi Inoue
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/02 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0097 , G11C2213/31 , G11C2213/71 , G11C2213/72
摘要： Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.
摘要翻译：一个实施例的非易失性半导体存储器件包括：存储单元阵列，包括彼此相交的多个第一和第二线，以及设置在第一和第二线的交点处的多个存储单元，并且在施加相同的电压时写入和擦除数据极性; 以及写入电路，被配置为选择第一和第二行，并且通过所选择的第一和第二行向存储器单元提供置位或复位脉冲。在擦除操作中，写入电路通过增加或减小复位区域内的复位脉冲的电压电平和电压施加时间，将复位脉冲重复地提供给所选择的存储单元，直到数据被擦除。复位区域或复位脉冲的电压电平和电压施加时间的组合的总和是电压电平和电压施加时间呈负相关的区域。

30. 发明授权

US07706171B2 Storage device 失效
标题翻译：储存设备
公开(公告)号：US07706171B2
公开(公告)日：2010-04-27
申请号：US11837097
申请日：2007-08-10
申请人： Kenichi Murooka
发明人： Kenichi Murooka
IPC分类号： G11C11/00
CPC分类号： G11C23/00 , G11C2213/71 , G11C2213/77
摘要： The present invention provides a storage device including a first electrode, a plurality of second electrodes arranged opposite the first electrode across a gap, and a particle which is selectively placed in one of the gaps between the first electrode and the second electrodes and which is movable between the first electrode and the second electrode and between the adjacent second electrodes. A stored state is determined utilizing the presence of the particle.
摘要翻译：本发明提供了一种存储装置，其包括第一电极，跨越间隙与第一电极相对布置的多个第二电极和选择性地放置在第一电极和第二电极之间的间隙之一中并且可移动的在第一电极和第二电极之间以及相邻的第二电极之间。使用颗粒的存在来确定存储状态。

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