专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20090039336A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090039336A1
公开(公告)日：2009-02-12
申请号：US12176606
申请日：2008-07-21
申请人： Motoyasu Terao , Yoshitaka Sasago , Kenzo Kurotsuchi , Kazuo Ono , Yoshihisa Fujisaki , Norikatsu Takaura , Riichiro Takemura
发明人： Motoyasu Terao , Yoshitaka Sasago , Kenzo Kurotsuchi , Kazuo Ono , Yoshihisa Fujisaki , Norikatsu Takaura , Riichiro Takemura
IPC分类号： H01L45/00
CPC分类号： G11C11/5614 , G11C13/0011 , G11C13/0069 , G11C2013/0083 , G11C2213/11 , G11C2213/15 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/1675
摘要： The performance of a semiconductor device capable of storing information is improved. A memory layer of a memory element is formed by a first layer at a bottom electrode side and a second layer at a top electrode side. The first layer contains 20-70 atom % of at least one element of a first element group of Cu, Ag, Au, Al, Zn, and Cd, contains 3-40 atom % of at least one element of a second element group of V, Nb, Ta, Cr, Mo, W, Ti, Zr, Hf, Fe, Co, Ni, Pt, Pd, Rh, Ir, Ru, Os, and lanthanoid elements, and contains 20-60 atom % of at least one element of a third element group of S, Se, and Te. The second layer contains 5-50 atom % of at least one element of the first element group, 10-50 atom % of at least one element of the second element group, and 30-70 atom % of oxygen.
摘要翻译：提高了能够存储信息的半导体装置的性能。存储元件的存储层由底部电极侧的第一层和顶部电极侧的第二层形成。第一层含有20-70原子％的Cu，Ag，Au，Al，Zn和Cd的第一元素基团的至少一种元素，含有3-40原子％的至少一种元素的第二元素基团 V，Nb，Ta，Cr，Mo，W，Ti，Zr，Hf，Fe，Co，Ni，Pt，Pd，Rh，Ir，Ru，Os和镧系元素，至少含有20-60原子％ S，Se和Te的第三要素组的一个元素。第二层含有5-50原子％的第一元素基团的至少一个元素，10-50原子％的第二元素基团的至少一个元素和30-70原子％的氧。

22. 发明授权

US06635913B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US06635913B2
公开(公告)日：2003-10-21
申请号：US10026615
申请日：2001-12-27
申请人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
发明人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
IPC分类号： H01L2976
CPC分类号： H01L28/75 , H01L28/55 , H01L28/57 , H01L28/60
摘要： The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively act as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.
摘要翻译：电容器的上电极由层叠膜构成，其用于防止氢原子到达电容器电极并降低性能。在一个示例中，四层上电极分别用作肖特基势垒层，氢扩散防止层，反应防止层和吸附抑制层。因此，可以防止由于还原气氛导致半导体器件中的电容下降，绝缘不良和电极剥离的发生。另外，可以提高装置的长期可靠性。

23. 发明授权

US06432767B1 Method of fabricating semiconductor device 有权
公开(公告)号：US06432767B1
公开(公告)日：2002-08-13
申请号：US09897615
申请日：2001-07-03
申请人： Kazuyoshi Torii , Hiroshi Kawakami , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Masahiro Moniwa
发明人： Kazuyoshi Torii , Hiroshi Kawakami , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Masahiro Moniwa
IPC分类号： H01L218242
摘要： A semiconductor device having a bottom electrode, a ferroelectric film, and a top electrode formed on a semiconductor substrate, wherein the angle of each of the main cross sectional sides of the ferroelectric film relative to the main surface of the semiconductor substrate is less than 75 degrees. Forming the ferroelectric film into the trapezoid in cross section having such an angle provides a microscopic capacitor without electrical short-circuit between the top and bottom electrodes if the top electrode, the ferroelectric film, and the bottom electrode are etched with single photolithography process step. The novel technique implements a microscopic memory cell structure suitable for highly integrated memory devices.

24. 发明授权

US06342712B1 Semiconductor storage device with ferrielectric capacitor and metal-oxide isolation 有权
标题翻译：具有电介质电容器和金属氧化物隔离的半导体存储器件
公开(公告)号：US06342712B1
公开(公告)日：2002-01-29
申请号：US09341523
申请日：1999-08-13
申请人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
发明人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
IPC分类号： H01L2992
CPC分类号： H01L28/75 , H01L28/55 , H01L28/57 , H01L28/60
摘要： The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively act as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.
摘要翻译：电容器的上电极由层叠膜构成，其用于防止氢原子到达电容器电极并降低性能。在一个示例中，四层上电极分别用作肖特基势垒层，氢扩散防止层，反应防止层和吸附抑制层。因此，可以防止由于还原气氛导致半导体器件中的电容下降，绝缘不良和电极剥离的发生。另外，可以提高装置的长期可靠性。

25. 发明授权

US6097051A Semiconductor device and method of fabricating 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US6097051A
公开(公告)日：2000-08-01
申请号：US755602
申请日：1996-11-25
申请人： Kazuyoshi Torii , Hiroshi Kawakami , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Masahiro Moniwa
发明人： Kazuyoshi Torii , Hiroshi Kawakami , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Masahiro Moniwa
IPC分类号： H01L21/8247 , H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： H01L28/55 , H01L27/10852
摘要： A semiconductor device having a bottom electrode, a ferroelectric film, and a top electrode formed on a semiconductor substrate, wherein the angle of each of the main cross sectional sides of the ferroelectric film relative to the main surface of the semiconductor substrate is less than 75 degrees. Forming the ferroelectric film into the trapezoid in cross section having such an angle provides a microscopic capacitor without electrical short-circuit between the top and bottom electrodes if the top electrode, the ferroelectric film, and the bottom electrode are etched with single photolithography process step. The novel technique implements a microscopic memory cell structure suitable for highly integrated memory devices.
摘要翻译：一种形成在半导体衬底上的具有底电极，铁电体膜和顶电极的半导体器件，其中，强电介质膜的每个主横截面相对于半导体衬底的主表面的角度小于75 度。如果用单一光刻工艺步骤蚀刻上电极，铁电体膜和底电极，则将铁电膜形成具有这种角度的横截面中的梯形，提供了在顶电极和底电极之间没有电短路的微电容器。该新技术实现了适用于高度集成的存储器件的微观存储单元结构。

26. 发明授权

US5481120A Semiconductor device and its fabrication method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5481120A
公开(公告)日：1996-01-02
申请号：US164801
申请日：1993-12-10
申请人： Kazuhiro Mochizuki , Tomoyoshi Mishima , Tohru Nakamura , Hiroshi Masuda , Tomonori Tanoue , Tooru Haga , Yoshihisa Fujisaki
发明人： Kazuhiro Mochizuki , Tomoyoshi Mishima , Tohru Nakamura , Hiroshi Masuda , Tomonori Tanoue , Tooru Haga , Yoshihisa Fujisaki
IPC分类号： H01L21/331 , H01L29/08 , H01L29/20 , H01L29/45 , H01L29/737 , H01L29/80 , H01S5/042 , H01S5/183 , H01S5/22 , H01S5/323 , H01L27/02
CPC分类号： H01S5/18347 , H01L29/0891 , H01L29/20 , H01L29/452 , H01L29/66318 , H01L29/7371 , H01S5/0424 , H01L29/802 , H01S2304/02 , H01S5/18341 , H01S5/18369 , H01S5/32316
摘要： Disclosed is a semiconductor device using a polycrystalline compound semiconductor with a low resistance as a low resistance layer, and its fabrication method. The above polycrystalline compound semiconductor layer is doped with C or Be as impurities in a large amount, and is extremely low in resistance. The polycrystalline compound semiconductor layer is formed by either of a molecular beam epitaxy method, an organometallic vapor phase epitaxy method and an organometallic molecular beam epitaxy method under the condition that a substrate temperature is 450.degree. C. or less and the ratio of partial pressure of a V-group element to a III-group element is 50 or more. In the case that the above polycrystaline compound semiconductor layer with a low resistance is used as an extrinsic base region of an heterojunction bipolar transistor, since the extrinsic base region can be formed on a dielectric film formed on a collector, it is possible to reduce the base-collector capacitance, and hence to enhance the operational speed of the heterojunction bipolar transistor.
摘要翻译：公开了使用具有低电阻的多晶化合物半导体作为低电阻层的半导体器件及其制造方法。上述多晶化合物半导体层以C或Be作为杂质被大量掺杂，并且电阻极低。多晶化合物半导体层通过分子束外延法，有机金属气相外延法和有机金属分子束外延法中的任一种形成，在基板温度为450℃以下的条件下，对于III族元素的V族元素为50以上。在上述具有低电阻的多晶化合物半导体层用作异质结双极晶体管的外在基极区域的情况下，由于可以在形成在集电体上的电介质膜上形成非本征基区，因此可以减少基极集电极电容，从而提高异质结双极晶体管的工作速度。

27. 发明授权

US07864568B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US07864568B2
公开(公告)日：2011-01-04
申请号：US12516690
申请日：2006-12-07
申请人： Yoshihisa Fujisaki , Satoru Hanzawa , Kenzo Kurotsuchi , Nozomu Matsuzaki , Norikatsu Takaura
发明人： Yoshihisa Fujisaki , Satoru Hanzawa , Kenzo Kurotsuchi , Nozomu Matsuzaki , Norikatsu Takaura
IPC分类号： G11C11/00
CPC分类号： H01L45/144 , G11C13/0004 , G11C13/0069 , G11C2213/75 , H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233
摘要： In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided. The semiconductor storage device includes a phase change thin film 101 having two stable phases of a crystal state with low electric resistance and an amorphous state with high electric resistance, upper plug electrodes 102 and 103 provided on one side of the phase change thin film 101, a lower electrode 104 provided on the other side of the phase change thin film 101, a selecting transistor 114 whose drain/source terminals are connected to the upper plug electrode 102 and the lower electrode 104, and a selecting transistor 115 whose drain/source terminals are connected to the upper plug electrode 103 and the lower electrode 104, and a first memory cell is configured with the selecting transistor 114 and a phase change region 111 in the phase change thin film 101 sandwiched between the upper plug electrode 102 and the lower electrode 104, and a second memory cell is configured with the selecting transistor 115 and a phase change region 112 in the phase change thin film 101 sandwiched between the upper plug electrode 103 and the lower electrode 104.
摘要翻译：在诸如相变存储器的半导体存储装置中，提供了可以实现高集成度的技术。半导体存储装置包括：具有低电阻的晶体状态的两个稳定相和具有高电阻的非晶态的相变薄膜101，设置在相变薄膜101一侧的上部插塞电极102和103，设置在相变薄膜101的另一侧的下部电极104，漏极/源极端子连接到上部插塞电极102和下部电极104的选择晶体管114，以及选择晶体管115，其漏极/源极端子连接到上插头电极103和下电极104，并且第一存储单元配置有夹在上插头电极102和下电极之间的相变薄膜101中的选择晶体管114和相变区域111 104，并且第二存储单元配置有夹在b中的相变薄膜101中的选择晶体管115和相变区域112 在上塞电极103和下电极104之间。

28. 发明申请

US20100096613A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100096613A1
公开(公告)日：2010-04-22
申请号：US12522744
申请日：2007-01-11
申请人： Takahiro Morikawa , Motoyasu Terao , Norikatsu Takaura , Kenzo Kurotsuchi , Nozomu Matsuzaki , Yoshihisa Fujisaki , Masaharu Kinoshita , Yuichi Matsui
发明人： Takahiro Morikawa , Motoyasu Terao , Norikatsu Takaura , Kenzo Kurotsuchi , Nozomu Matsuzaki , Yoshihisa Fujisaki , Masaharu Kinoshita , Yuichi Matsui
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/144 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony.
摘要翻译：相变存储器由形成在半导体衬底上的绝缘膜中的埋入通孔内的插塞形成，形成在绝缘膜上的界面层，其中埋入插塞，由硫化物层形成的记录层形成在界面层和形成在记录层上的上接触电极。根据电阻值变化存储信息的记录层由含有20原子％至38原子％的量的铟的含量为9原子％至28原子％的锗的硫属化物材料制成，3原子级的锑％〜18原子％，碲为42原子％〜63原子％，锗的含量大于或等于锑的含量。

29. 发明授权

US07033958B2 Semiconductor device and process for producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07033958B2
公开(公告)日：2006-04-25
申请号：US10649613
申请日：2003-08-28
申请人： Yoshihisa Fujisaki , Hiroshi Ishihara
发明人： Yoshihisa Fujisaki , Hiroshi Ishihara
IPC分类号： H01L21/31
CPC分类号： H01L21/28185 , H01L21/28202 , H01L29/513 , H01L29/518
摘要： A semiconductor apparatus is provided that is thermally stable in a post process and is suitable for fabricating a gate insulator having a laminated structure with various high permittivity oxides, and a process is provided for producing the same. In order to achieve a high function formation of a gate insulator, a silicon nitride film having a specific inductive capacity approximately twice as much as that of silicon oxide, and which is thermally stable, is not provided with a Si—H bond and is used as at least a portion of the gate insulator. Further, an effective thickness of a gate insulator forming a multilayered structure insulator laminated with a metal oxide having a high dielectric constant, in conversion to silicon oxide, can be thinned to less than 3 nm while restraining leakage current.
摘要翻译：提供了一种在后工序中热稳定的半导体装置，并且适用于制造具有各种高介电常数氧化物的层叠结构的栅极绝缘体，并且提供了制造其的工艺。为了实现栅极绝缘体的高功能性形成，具有比氧化硅大约是电化学氧化硅的比电感容量大约是其热稳定性的两倍的氮化硅膜不具有Si-H键并且被使用作为栅极绝缘体的至少一部分。此外，形成层叠有具有高介电常数的金属氧化物的多层结构绝缘体的栅极绝缘体的有效厚度可以在抑制漏电流的同时变薄到小于3nm。

30. 发明授权

US06822276B1 Memory structure with a ferroelectric capacitor 失效
标题翻译：具有铁电电容的存储器结构
公开(公告)号：US06822276B1
公开(公告)日：2004-11-23
申请号：US09391250
申请日：1999-09-07
申请人： Kazuyoshi Torii , Hiroshi Miki , Yoshihisa Fujisaki
发明人： Kazuyoshi Torii , Hiroshi Miki , Yoshihisa Fujisaki
IPC分类号： H01L27108
CPC分类号： H01L28/56 , H01L21/28568 , H01L27/10852 , H01L27/10855 , H01L28/55 , H01L28/75
摘要： It is an object of the present invention to provide a fine memory cell structure preventing a reaction between an interlayer insulating film and a ferroelectric film and suitable for high integration. According to the invention, there is provided a structure in which a reaction barrier film 43 is interposed between a ferroelectric film 71 and an interlayer insulating film 32 and side walls of a diffusion barrier film 51 are not brought into direct contact with the ferroelectric film 71. Thereby, the reaction between the interlayer insulating film 32 and the ferroelectric film 71 can be restrained and exfoliation of the ferroelectric film 71 can be prevented.
摘要翻译：本发明的目的是提供一种防止层间绝缘膜和铁电体膜之间的反应并且适合于高集成度的精细存储单元结构。根据本发明，提供一种结构，其中反应阻挡膜43介于铁电膜71和层间绝缘膜32之间，并且扩散阻挡膜51的侧壁不与铁电体膜71直接接触由此，能够抑制层间绝缘膜32与强电介质膜71的反应，能够防止铁电体膜71的剥离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式