专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20070169009A1 Method and system for outputting a sequence of commands and data described by a flowchart 有权
标题翻译：用于输出由流程图描述的命令和数据序列的方法和系统
公开(公告)号：US20070169009A1
公开(公告)日：2007-07-19
申请号：US11260517
申请日：2005-10-27
申请人： Andrey Nikitin , Alexander Andreev , Ranko Scepanovic
发明人： Andrey Nikitin , Alexander Andreev , Ranko Scepanovic
IPC分类号： G06F9/45
CPC分类号： G06F8/66
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译：本发明是用于输出由流程图描述的命令和数据序列的方法和系统。该方法包括以下步骤。接收描述命令和数据序列的流程图。流程图包括多个流程图符号。多个流程图符号中的每一个被分配有ROM（只读存储器）记录。分配的ROM记录存储在ROM中。产生处理器以包括ROM，其中处理器接收CLOCK信号，RESET信号，ENABLE信号和N个二进制输入x 1，x 2，。。。并且输出命令和数据的序列。

22. 发明申请

US20050086624A1 Process and apparatus for fast assignment of objects to a rectangle 有权
标题翻译：将对象快速分配给矩形的过程和设备
公开(公告)号：US20050086624A1
公开(公告)日：2005-04-21
申请号：US10688460
申请日：2003-10-17
申请人： Alexander Andreev , Andrey Nikitin , Ranko Scepanovic
发明人： Alexander Andreev , Andrey Nikitin , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Objects are assigned to points in a rectangle by dividing the rectangle is divided into a plurality of smaller rectangles and applying an object assignment procedure, such as Kuhn's algorithm, to initially assigned objects in each second rectangle. The initial assignment is performed by calculating a maximal cost of assignment of objects to points, and selecting an assignment of objects having a minimum value of maximal cost, identified by iteratively recalculating the maximal matching assignment based on a midpoint of between the minimum and maximum costs.
摘要翻译：通过将矩形划分为多个较小的矩形并将对象分配过程（例如Kuhn算法）应用于每个第二矩形中的初始分配对象，将对象分配给矩形中的点。通过计算对象到点的分配的最大成本并且选择具有最大成本的最小值的对象的分配来执行初始分配，通过基于最小和最大成本之间的中点迭代地重新计算最大匹配分配来识别。

23. 发明授权

US08239813B2 Method and apparatus for balancing signal delay skew 失效
标题翻译：信号延迟偏移平衡的方法和装置
公开(公告)号：US08239813B2
公开(公告)日：2012-08-07
申请号：US13173855
申请日：2011-06-30
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykih , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykih , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.
摘要翻译：根据各种实施例，提供了一种用于减少信号延迟偏差的系统和方法。本公开的一个说明性实施例涉及一种方法。根据一个说明性实施例，该方法包括：接收在组件之间具有组件和连接路径的初始网表; 识别所述初始网表中的第一连接路径，其包括在所述初始网表中的第二连接路径中不存在等效路径片段的路径片段; 生成偏差校正网表，其中所述第二连接路径被重新路由以具有等同于所述第一连接路径的路径片段的路径片段; 并输出偏差校正的网表。

24. 发明申请

US20070044053A1 Multimode delay analyzer 失效
标题翻译：多模延迟分析仪
公开(公告)号：US20070044053A1
公开(公告)日：2007-02-22
申请号：US11205365
申请日：2005-08-17
申请人： Alexander Andreev , Andrey Nikitin , Ranko Scepanovic
发明人： Alexander Andreev , Andrey Nikitin , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, by inputting a net list, IO arc delays, interconnection arc delays, and constant nets with assigned Boolean functions for the integrated circuit design, propagating the constant nets and assigning Boolean conditions to the IO arc delays and the interconnection arc delays, evaluating timing path delays and conditions for the integrated circuit design, creating the integrated circuit design timing model parameters, and outputting the integrated circuit design timing model. The method is especially desirable for netlists with very complicated mixing logics that include muxing of clocks. In particular, RRAMs are such netlists.
摘要翻译：一种分析集成电路设计中的多模延迟的方法，通过输入集成电路设计的网络列表，IO弧延迟，互连电弧延迟和具有分配布尔函数的恒定网络来生成集成电路设计的定时模型，传播恒定网络和布尔条件给IO弧延迟和互连电弧延迟，评估集成电路设计的定时路径延迟和条件，创建集成电路设计时序模型参数，并输出集成电路设计时序模型。该方法对于具有非常复杂的混合逻辑（包括时钟复用）的网表来说是特别需要的。特别地，RRAM是这样的网表。

25. 发明申请

US20120278783A1 SIGNAL DELAY SKEW REDUCTION SYSTEM 失效
标题翻译：信号延迟减少系统
公开(公告)号：US20120278783A1
公开(公告)日：2012-11-01
申请号：US13544632
申请日：2012-07-09
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.
摘要翻译：提供了一种减少信号偏移的系统和方法。该方法包括接收具有组件之间的组件和连接的网表。每个连接具有至少一个信号线。识别多个网络组，每个网络组包括至少一些连接并且期望等效路由。对于每个网络组，所述方法包括系统地路由用于连接的组件之间的连接路径，每个连接路径在组件之一的输出和至少一个其他组件的输入之间延伸并且包括至少一个路径片段。对于网络组的至少一个连接，路由包括在与连接路径的路径片段中的至少一个相邻并且平行的路由信道中路由至少一个接地屏蔽线。

26. 发明授权

US07512918B2 Multimode delay analysis for simplifying integrated circuit design timing models 失效
标题翻译：用于简化集成电路设计时序模型的多模延迟分析
公开(公告)号：US07512918B2
公开(公告)日：2009-03-31
申请号：US11205365
申请日：2005-08-17
申请人： Alexander Andreev , Andrey Nikitin , Ranko Scepanovic
发明人： Alexander Andreev , Andrey Nikitin , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of analyzing multimode delay in an integrated circuit design to produce a timing model for the integrated circuit design, by inputting a net list, IO arc delays, interconnection arc delays, and constant nets with assigned Boolean functions for the integrated circuit design, propagating the constant nets and assigning Boolean conditions to the IO arc delays and the interconnection arc delays, evaluating timing path delays and conditions for the integrated circuit design, creating the integrated circuit design timing model parameters, and outputting the integrated circuit design timing model. The method is especially desirable for netlists with very complicated mixing logics that include muxing of clocks. In particular, RRAMs are such netlists.
摘要翻译：一种分析集成电路设计中的多模延迟的方法，通过输入集成电路设计的网络列表，IO弧延迟，互连电弧延迟和具有分配布尔函数的恒定网络来生成集成电路设计的定时模型，传播恒定网络和布尔条件给IO弧延迟和互连电弧延迟，评估集成电路设计的定时路径延迟和条件，创建集成电路设计时序模型参数，并输出集成电路设计时序模型。该方法对于具有非常复杂的混合逻辑（包括时钟复用）的网表来说是特别需要的。特别地，RRAM是这样的网表。

27. 发明申请

US20060117281A1 Verification of RRAM tiling netlist 失效
标题翻译：验证RRAM平铺网表
公开(公告)号：US20060117281A1
公开(公告)日：2006-06-01
申请号：US10999468
申请日：2004-11-30
申请人： Andrey Nikitin , Alexander Andreev , Ranko Scepanovic
发明人： Andrey Nikitin , Alexander Andreev , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part” of all nets and cells of a RRAM tiling netlist are set to a value 0. A boolean function 0 is assigned to all ground nets of the RRAM tiling netlist, and a boolean function 1 is assigned to all power nets of the RRAM tiling netlist. The RRAM tiling netlist is verified for each customer memory Memk, k=1, 2, . . . , N.
摘要翻译：本发明提供了一种RRAM拼接网表的验证方法。该方法可以包括以下步骤。属性RRAM平铺网表的所有网络和单元的“memory_number”，“clock_number”和“netlist_part”被设置为值0。布尔函数0被分配给RRAM平铺网表的所有接地网，并且布尔函数1被分配给RRAM平铺网表的所有电网。对于每个客户存储器验证RRAM平铺网表，其中k = 1,2，...。。。，N.

28. 发明申请

US20060020927A1 Method and system for outputting a sequence of commands and data described by a flowchart 失效
标题翻译：用于输出由流程图描述的命令和数据序列的方法和系统
公开(公告)号：US20060020927A1
公开(公告)日：2006-01-26
申请号：US10894781
申请日：2004-07-20
申请人： Alexander Andreev , Andrey Nikitin , Ranko Scepanovic
发明人： Alexander Andreev , Andrey Nikitin , Ranko Scepanovic
IPC分类号： G06F9/45
CPC分类号： G06F17/5054
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. In an exemplary aspect of the present invention, a method for outputting a sequence of commands and data described by a flowchart includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A module (e.g., a CKD, or the like) is generated to include the ROM, wherein the module receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译：本发明是用于输出由流程图描述的命令和数据序列的方法和系统。在本发明的一个示例性方面，用于输出由流程图描述的命令和数据序列的方法包括以下步骤。接收描述命令和数据序列的流程图。流程图包括多个流程图符号。多个流程图符号中的每一个被分配有ROM（只读存储器）记录。分配的ROM记录存储在ROM中。生成模块（例如，CKD等）以包括ROM，其中模块接收CLOCK信号，RESET信号，ENABLE信号和N个二进制输入x 1， x 2，...，。。并且输出命令和数据的序列。

29. 发明申请

US20060010092A1 Yield driven memory placement system 有权
标题翻译：产量驱动记忆放置系统
公开(公告)号：US20060010092A1
公开(公告)日：2006-01-12
申请号：US10875128
申请日：2004-06-23
申请人： Alexander Andreev , Andrey Nikitin , Ranko Scepanovic
发明人： Alexander Andreev , Andrey Nikitin , Ranko Scepanovic
IPC分类号： G11B23/20 , G11B5/02 , G11B5/10 , G06F17/00 , G06F17/50
CPC分类号： G06F17/5045 , G06F12/0292 , G06Q10/0875 , G06Q99/00
摘要： A user-defined memory design is mapped to memories of a base platform for an IC that contains a plurality of memory sets, each containing a plurality of memories of a predetermined type. An optimal memory set is selected from the plurality of memory sets for the design by selecting a preference rate for each memory set from the plurality of sets based on the design and its connections to portions of the IC, and selectively assigning the design to one of the memory sets based on the preference rate. The design is optimally mapped to a plurality of memories of the selected memory set by defining an index of the position of each customer memory in the selected memory set. The customer memories in the selected memory set are arranged in an order, and successive numbers of memories of the selected memory set are assigned to each customer memory in order.
摘要翻译：用户定义的存储器设计被映射到用于IC的基础平台的存储器，该存储器包含多个存储器组，每个存储器组包含预定类型的多个存储器。从设计的多个存储器集合中选择最佳存储器集合，其基于设计及其与IC的部分的连接，从多个集合中选择每个存储器组的偏好率，并且将该设计选择性地分配给基于优先级的内存集。通过定义所选择的存储器组中的每个顾客存储器的位置的索引，将设计最佳地映射到所选存储器组的多个存储器。所选择的存储器组中的客户存储器按顺序排列，并且所选择的存储器组的连续数量的存储器按顺序分配给每个客户存储器。

30. 发明申请

US20070094621A1 Method and system for converting netlist of integrated circuit between libraries 失效
标题翻译：图书馆集成电路网表的转换方法及系统
公开(公告)号：US20070094621A1
公开(公告)日：2007-04-26
申请号：US11257206
申请日：2005-10-24
申请人： Pavel Panteleev , Andrey Nikitin , Alexander Andreev
发明人： Pavel Panteleev , Andrey Nikitin , Alexander Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present invention provides a method for converting a netlist of an integrated circuit from a first library to a second library. The first library may include logic cells AND, OR and NOT, and the second library may include logic cells NAND and NOR. The method includes steps as follows. Logic cells of the netlist are topologically sorted from outputs to inputs. AND and OR cells of the netlist are replaced with NOT, NAND and NOR cells. Simplification of the netlist is performed in a topological order.
摘要翻译：本发明提供一种用于将集成电路的网表从第一库转换为第二库的方法。第一个库可以包括逻辑单元AND，OR和NOT，并且第二库可以包括逻辑单元NAND和NOR。该方法包括以下步骤。网表的逻辑单元从输出到输入进行拓扑分类。将网表的AND和OR单元替换为NOT，NAND和NOR单元。网表的简化是以拓扑顺序执行的。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式