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1. 发明授权

US08239813B2 Method and apparatus for balancing signal delay skew 失效
标题翻译：信号延迟偏移平衡的方法和装置
公开(公告)号：US08239813B2
公开(公告)日：2012-08-07
申请号：US13173855
申请日：2011-06-30
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykih , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykih , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.
摘要翻译：根据各种实施例，提供了一种用于减少信号延迟偏差的系统和方法。本公开的一个说明性实施例涉及一种方法。根据一个说明性实施例，该方法包括：接收在组件之间具有组件和连接路径的初始网表; 识别所述初始网表中的第一连接路径，其包括在所述初始网表中的第二连接路径中不存在等效路径片段的路径片段; 生成偏差校正网表，其中所述第二连接路径被重新路由以具有等同于所述第一连接路径的路径片段的路径片段; 并输出偏差校正的网表。

2. 发明授权

US08516425B2 Method and computer program for generating grounded shielding wires for signal wiring 失效
标题翻译：用于生成信号线接地屏蔽线的方法和计算机程序
公开(公告)号：US08516425B2
公开(公告)日：2013-08-20
申请号：US13544632
申请日：2012-07-09
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykih , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykih , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.
摘要翻译：提供了一种减少信号偏移的系统和方法。该方法包括接收具有组件之间的组件和连接的网表。每个连接具有至少一个信号线。识别多个网络组，每个网络组包括至少一些连接并且期望等效路由。对于每个网络组，所述方法包括系统地路由用于连接的组件之间的连接路径，每个连接路径在组件之一的输出和至少一个其他组件的输入之间延伸并且包括至少一个路径片段。对于网络组的至少一个连接，路由包括在与连接路径的路径片段中的至少一个相邻并且平行的路由信道中路由至少一个接地屏蔽线。

3. 发明授权

US07996804B2 Signal delay skew reduction system 有权
标题翻译：信号延迟偏差减少系统
公开(公告)号：US07996804B2
公开(公告)日：2011-08-09
申请号：US12015925
申请日：2008-01-17
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykih , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykih , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.
摘要翻译：根据各种实施例，公开了一种用于减小信号延迟偏差的系统。本公开的一个说明性实施例涉及一种方法。根据一个说明性实施例，该方法包括接收包括组件之间的组件和连接路径的初始网表。该方法还包括识别在初始网表中的第一连接路径中的一个或多个偏斜影响特征，其在初始网表中的第二连接路径中缺少相应的偏斜影响特征。该方法还包括生成偏差校正网表，其中第二连接路径包括与第一连接路径的相应的一个或多个相加的偏斜影响特征。该方法还包括输出经偏斜校正的网表。

4. 发明申请

US20110258587A1 SIGNAL DELAY SKEW REDUCTION SYSTEM 失效
标题翻译：信号延迟减少系统
公开(公告)号：US20110258587A1
公开(公告)日：2011-10-20
申请号：US13173855
申请日：2011-06-30
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.
摘要翻译：根据各种实施例，提供了一种用于减少信号延迟偏差的系统和方法。本公开的一个说明性实施例涉及一种方法。根据一个说明性实施例，该方法包括：接收在组件之间具有组件和连接路径的初始网表; 识别所述初始网表中的第一连接路径，其包括在所述初始网表中的第二连接路径中不存在等效路径片段的路径片段; 生成偏差校正网表，其中所述第二连接路径被重新路由以具有等同于所述第一连接路径的路径片段的路径片段; 并输出偏差校正的网表。

5. 发明申请

US20090187873A1 SIGNAL DELAY SKEW REDUCTION SYSTEM 有权
标题翻译：信号延迟减少系统
公开(公告)号：US20090187873A1
公开(公告)日：2009-07-23
申请号：US12015925
申请日：2008-01-17
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.
摘要翻译：根据各种实施例，公开了一种用于减小信号延迟偏差的系统。本公开的一个说明性实施例涉及一种方法。根据一个说明性实施例，该方法包括接收包括组件之间的组件和连接路径的初始网表。该方法还包括识别在初始网表中的第一连接路径中的一个或多个偏斜影响特征，其在初始网表中的第二连接路径中缺少对应的偏斜影响特征。该方法还包括生成偏差校正网表，其中第二连接路径包括与第一连接路径的相应的一个或多个相加的偏斜影响特征。该方法还包括输出经偏斜校正的网表。

6. 发明申请

US20120278783A1 SIGNAL DELAY SKEW REDUCTION SYSTEM 失效
标题翻译：信号延迟减少系统
公开(公告)号：US20120278783A1
公开(公告)日：2012-11-01
申请号：US13544632
申请日：2012-07-09
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.
摘要翻译：提供了一种减少信号偏移的系统和方法。该方法包括接收具有组件之间的组件和连接的网表。每个连接具有至少一个信号线。识别多个网络组，每个网络组包括至少一些连接并且期望等效路由。对于每个网络组，所述方法包括系统地路由用于连接的组件之间的连接路径，每个连接路径在组件之一的输出和至少一个其他组件的输入之间延伸并且包括至少一个路径片段。对于网络组的至少一个连接，路由包括在与连接路径的路径片段中的至少一个相邻并且平行的路由信道中路由至少一个接地屏蔽线。

7. 发明申请

US20060288175A1 Feedback programmable data strobe enable architecture for DDR memory applications 有权
标题翻译：用于DDR存储器应用的反馈可编程数据选通使能架构
公开(公告)号：US20060288175A1
公开(公告)日：2006-12-21
申请号：US11154401
申请日：2005-06-16
申请人： Hui-Yin Seto , Derrick Butt , Cheng-Gang Kong
发明人： Hui-Yin Seto , Derrick Butt , Cheng-Gang Kong
IPC分类号： G06F13/00
CPC分类号： G06F13/4239
摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to read and write data through a plurality of input/output lines. The second circuit may include a plurality of sections. Each section may be configured to present a control signal to a load output line and receive a feedback of the control signal through a load input line. The load input line and the load output line of each of the sections may be connected to a load circuit configured to match a respective memory load connected to each of the plurality of input/output lines.
摘要翻译：一种包括第一电路和第二电路的装置。第一电路可以被配置为通过多个输入/输出线读取和写入数据。第二电路可以包括多个部分。每个部分可以被配置为向负载输出线呈现控制信号，并通过负载输入线接收控制信号的反馈。每个部分的负载输入线和负载输出线可以连接到被配置为匹配连接到多个输入/输出线中的每一个的相应存储器负载的负载电路。

8. 发明授权

US08230143B2 Memory interface architecture for maximizing access timing margin 失效
标题翻译：存储器接口架构，用于最大化访问时序裕量
公开(公告)号：US08230143B2
公开(公告)日：2012-07-24
申请号：US11097903
申请日：2005-04-01
申请人： Hui-Yin Seto , Cheng-Gang Kong
发明人： Hui-Yin Seto , Cheng-Gang Kong
IPC分类号： G06F13/10
CPC分类号： G06F13/1689
摘要： An apparatus comprising a control circuit, a buffer circuit and a memory. The control circuit may be configured to present a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate. The second signal in each of the pairs comprises a clock signal operating at the second data rate. The buffer circuit may be configured to generate a buffered signal in response to each of the pairs of signals. Each of the buffered signals operates at the second data rate. The memory may be configured to read and write data at the second data rate in response to the buffered signals.
摘要翻译：一种包括控制电路，缓冲电路和存储器的装置。控制电路可以被配置为响应于（i）以第一数据速率操作的一个或多个输入信号和（ii）以第二数据速率操作的输入时钟信号，呈现多对信号对。每对中的第二信号包括以第二数据速率操作的时钟信号。缓冲电路可以被配置为响应于每对信号产生缓冲信号。每个缓冲信号以第二数据速率工作。存储器可以被配置为响应于缓冲的信号以第二数据速率读取和写入数据。

9. 发明申请

US20060224847A1 Memory interface architecture for maximizing access timing margin 失效
标题翻译：存储器接口架构，用于最大化访问时序裕量
公开(公告)号：US20060224847A1
公开(公告)日：2006-10-05
申请号：US11097903
申请日：2005-04-01
申请人： Hui-Yin Seto , Cheng-Gang Kong
发明人： Hui-Yin Seto , Cheng-Gang Kong
IPC分类号： G06F13/00
CPC分类号： G06F13/1689
摘要： An apparatus comprising a control circuit, a buffer circuit and a memory. The control circuit may be configured to present a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate. The second signal in each of the pairs comprises a clock signal operating at the second data rate. The buffer circuit may be configured to generate a buffered signal in response to each of the pairs of signals. Each of the buffered signals operates at the second data rate. The memory may be configured to read and write data at the second data rate in response to the buffered signals.
摘要翻译：一种包括控制电路，缓冲电路和存储器的装置。控制电路可以被配置为响应于（i）以第一数据速率操作的一个或多个输入信号和（ii）以第二数据速率操作的输入时钟信号，呈现多对信号对。每对中的第二信号包括以第二数据速率操作的时钟信号。缓冲电路可以被配置为响应于每对信号产生缓冲信号。每个缓冲信号以第二数据速率工作。存储器可以被配置为响应于缓冲的信号以第二数据速率读取和写入数据。

10. 发明授权

US08819354B2 Feedback programmable data strobe enable architecture for DDR memory applications 有权
标题翻译：用于DDR存储器应用的反馈可编程数据选通使能架构
公开(公告)号：US08819354B2
公开(公告)日：2014-08-26
申请号：US11154401
申请日：2005-06-16
申请人： Hui-Yin Seto , Derrick Sai-Tang Butt , Cheng-Gang Kong
发明人： Hui-Yin Seto , Derrick Sai-Tang Butt , Cheng-Gang Kong
IPC分类号： G06F12/00
CPC分类号： G06F13/4239
摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to read and write data through a plurality of input/output lines. The second circuit may include a plurality of sections. Each section may be configured to present a control signal to a load output line and receive a feedback of the control signal through a load input line. The load input line and the load output line of each of the sections may be connected to a load circuit configured to match a respective memory load connected to each of the plurality of input/output lines.
摘要翻译：一种包括第一电路和第二电路的装置。第一电路可以被配置为通过多个输入/输出线读取和写入数据。第二电路可以包括多个部分。每个部分可以被配置为向负载输出线呈现控制信号，并通过负载输入线接收控制信号的反馈。每个部分的负载输入线和负载输出线可以连接到被配置为匹配连接到多个输入/输出线中的每一个的相应存储器负载的负载电路。

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