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21. 发明授权

US07827513B2 Buffer placement with respect to data flow direction and placement area geometry in hierarchical VLS designs 有权
标题翻译：相对于分层VLS设计中的数据流方向和放置区几何的缓冲放置
公开(公告)号：US07827513B2
公开(公告)日：2010-11-02
申请号：US11870728
申请日：2007-10-11
申请人： Joseph J. Palumbo , Christopher J. Berry , Adam R. Jalkowski
发明人： Joseph J. Palumbo , Christopher J. Berry , Adam R. Jalkowski
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for identifying and modifying, in a VLSI hierarchical chip design, parent buffer placements which lead to wiring track inefficiencies with respect to data flow and the parent placement area geometry. Parent placement area is reviewed and a subset is categorized and distinguished as either horizontal slots or vertical slots. Buffer to buffer data flow is reviewed for cases where data flow direction is either strongly horizontal or strongly vertical. Situations where buffer to buffer data flow is oriented in the same direction as the parent placement slots in which the buffers reside are reported. Additionally, an attempt is made to find a valid placement location for the buffers excluding parent placement areas oriented in the same direction as the data flow.
摘要翻译：用于在VLSI分级芯片设计中识别和修改父缓冲区布置的方法，其导致布线跟踪关于数据流和父放置区几何的低效。审查父放置区域，并将子集分类为区分为水平插槽或垂直插槽。对数据流方向是强水平或强垂直的情况进行缓冲数据流的缓冲。报告缓冲区缓冲区数据流向与缓冲区驻留的父放置槽方向相同的方向的情况。另外，试图找到除了排列方向与数据流相同方向的父放置区之外的缓冲区的有效放置位置。

22. 发明申请

US20070300095A1 Double Data Rate Chaining for Synchronous DDR Interfaces 失效
标题翻译：双数据速率链接同步DDR接口
公开(公告)号：US20070300095A1
公开(公告)日：2007-12-27
申请号：US11426651
申请日：2006-06-27
申请人： Michael Fee , Patrick J. Meaney , Christopher J. Berry , Jonathan Y. Chen , Alan P. Wagstaff
发明人： Michael Fee , Patrick J. Meaney , Christopher J. Berry , Jonathan Y. Chen , Alan P. Wagstaff
IPC分类号： G06F1/12
CPC分类号： G06F13/4217
摘要： A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.
摘要翻译：一种系统和方法，其中接收芯片分别锁存从双数据速率总线接收的数据的每一半。每一半都可以立即启动; 一个在正常的芯片周期时间，另一个从主（L1）锁存器半个周期启动到正常的芯片周期时间。首先推出的一半数据通过芯片沿其标准设计芯片路径进行，由芯片驱动接口锁存器捕获，并在芯片上的一个延迟周期后再次启动。数据的后半部分通过芯片在上半部分后半个周期进行，并且稍后通过进入从（L2）锁存器的路径被锁存半个时钟周期。在本地时钟的下一个边缘，数据然后从L2锁存器继续到驱动双数据速率接口。这允许半周期的半周期设置时间，以便可以再次启动，在芯片上保持一个周期的时间。

23. 发明授权

US06277431B1 Anticholesterolemic edible oil 失效
标题翻译：抗胆固醇油食用油
公开(公告)号：US06277431B1
公开(公告)日：2001-08-21
申请号：US09411591
申请日：1999-10-04
申请人： Christopher J. Berry , Marvin L. Bierenbaum
发明人： Christopher J. Berry , Marvin L. Bierenbaum
IPC分类号： A23D7005
CPC分类号： A23D9/007 , A23L33/11 , A23L33/115
摘要： An edible oil is provided that decreases the synthesis, absorption and blood level of cholesterol by a human patient, increases the excretion of cholesterol from the human patient, curtails accumulation of peroxidized material in the blood of the human patient, and also increases the blood level of vitamin E in said human patient.
摘要翻译：提供食用油，其降低人类患者胆固醇的合成，吸收和血液水平，增加人类患者胆固醇的排泄，将过氧化物质累积在人类患者的血液中，并且还增加血液水平的维生素E。

24. 发明授权

US5064681A Selective deposition process for physical vapor deposition 失效
标题翻译：物理气相沉积的选择性沉积工艺
公开(公告)号：US5064681A
公开(公告)日：1991-11-12
申请号：US364071
申请日：1989-06-08
申请人： Christopher J. Berry , Jerome J. Cuomo , C. Richard Guarnieri , Dennis S. Yee
发明人： Christopher J. Berry , Jerome J. Cuomo , C. Richard Guarnieri , Dennis S. Yee
IPC分类号： C23C14/04 , C23C14/22 , H01L21/20 , H01L21/268 , H01L21/3205 , H05K3/14
CPC分类号： H01L21/32051 , C23C14/048 , C23C14/22 , H01L21/268 , H05K3/146
摘要： The invention relates to a dry method for depositing a material on a substrate having nucleating sites for the material which includes deposition of a material in the vapor phase on the substrate and simultaneous ablation of the substrate by ablation methods for controlled removal of the nucleating sites from the substrate. The removal of the nucleating sites is controlled to minimize or selectively prevent coating of the substrate by the material. The method can be used to form material patterns on the substrate such as electrical circuits or for adhering material to a substrate that is difficult to metallize such as organic polymers or ceramics.
摘要翻译：本发明涉及一种用于在材料上沉积材料的干法，该材料具有用于材料的成核位置，该材料包括在衬底上沉积气相中的材料，并通过消融方法同时消除基底，从而控制将成核位点从底物。控制成核部位的去除以最小化或选择性地防止材料对基材的涂覆。该方法可以用于在诸如电路的基板上形成材料图案，或用于将材料粘附到难以金属化的基板上，例如有机聚合物或陶瓷。

25. 发明授权

US09466545B1 Semiconductor package in package 有权
标题翻译：半导体封装封装
公开(公告)号：US09466545B1
公开(公告)日：2016-10-11
申请号：US11677506
申请日：2007-02-21
申请人： Christopher M. Scanlan , Christopher J. Berry
发明人： Christopher M. Scanlan , Christopher J. Berry
IPC分类号： H01L33/00 , H01L23/31 , H01L21/56
CPC分类号： H01L23/552 , H01L21/56 , H01L21/561 , H01L21/568 , H01L23/3121 , H01L23/3135 , H01L23/5385 , H01L23/5386 , H01L23/5389 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/97 , H01L25/03 , H01L25/105 , H01L25/16 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/81005 , H01L2224/81913 , H01L2224/83005 , H01L2224/85005 , H01L2224/85913 , H01L2224/97 , H01L2924/00014 , H01L2924/14 , H01L2924/15151 , H01L2924/15313 , H01L2924/181 , H01L2924/19105 , H01L2924/19107 , H01L2924/3025 , H05K1/0216 , H05K1/181 , H01L2924/00012 , H01L2224/83 , H01L2224/81 , H01L2224/85 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor package having a second semiconductor package or module integrated therein. The semiconductor package of the present invention typically comprises active and passive devices which are each electrically connected to an underlying substrate. The substrate is configured to place such active and passive devices into electrical communication with contacts of the substrate disposed on a surface thereof opposite that to which the active and passive devices are mounted. The module of the semiconductor package resides within a complimentary opening disposed within the substrate thereof. The module and the active and passive devices of the semiconductor package are each fully or at least partially covered by a package body of the semiconductor package.
摘要翻译：一种具有集成在其中的第二半导体封装或模块的半导体封装。本发明的半导体封装通常包括有源和无源器件，它们各自电连接到下面的衬底。衬底被配置为将这种有源和无源器件与设置在与安装有源和无源器件的表面相反的表面上的衬底的触点电连通。半导体封装的模块位于设置在其基板内的互补开口内。半导体封装的模块和有源和无源器件都被半导体封装的封装主体全部或至少部分地覆盖。

26. 发明授权

US07921399B2 Method for simplifying tie net modeling for router performance 有权
标题翻译：简化路由器性能的联网建模的方法
公开(公告)号：US07921399B2
公开(公告)日：2011-04-05
申请号：US12032823
申请日：2008-02-18
申请人： Christopher J. Berry , Michael Alexander Bowen
发明人： Christopher J. Berry , Michael Alexander Bowen
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for preprocessing tie net routing data organizes the data into a plurality of tie nets each based on an optimal connection path between a pin or set of pins and the power grid. The router then routs the data embodying the thusly-simplified plurality of tie nets. Once the routing is complete, post processor takes the routed design and returns it to its original net list state while keeping the routing solution.
摘要翻译：一种用于预处理联网网络路由数据的方法将数据组织成多个连接网络，每个连接网络基于引脚或引脚组与电网之间的最佳连接路径。然后，路由器路由体现由此简化的多个连接网络的数据。路由完成后，后处理器采用路由设计，并将其恢复到原始的网络列表状态，同时保持路由解决方案。

27. 发明授权

US07882322B2 Early directory access of a double data rate elastic interface 失效
标题翻译：早期目录访问的双倍数据速率弹性界面
公开(公告)号：US07882322B2
公开(公告)日：2011-02-01
申请号：US11426675
申请日：2006-06-27
申请人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
发明人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/4059 , G06F12/0855 , G06F12/0864
摘要： A system and method to organize and use data sent over a double data rate interface so that the system operation does not experience a time penalty. The first cycle of data is used independently of the second cycle so that latency is not jeopardized. There are many applications. In a preferred embodiment for an L2 cache, the system transmits congruence class data in the first half and can start to access the L2 cache directory with the congruence class data.
摘要翻译：一种用于组织和使用通过双数据速率接口发送的数据的系统和方法，使得系统操作不会经历时间惩罚。数据的第一个循环独立于第二个周期使用，以便等待时间不会受到损害。有很多应用程序。在L2高速缓存的优选实施例中，系统在前半部分发送同余类数据，并且可以开始以一致类数据访问L2高速缓存目录。

28. 发明授权

US07752475B2 Late data launch for a double data rate elastic interface 失效
标题翻译：推迟数据速率的双倍数据速率弹性界面
公开(公告)号：US07752475B2
公开(公告)日：2010-07-06
申请号：US11426671
申请日：2006-06-27
申请人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
发明人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
IPC分类号： G06F13/00 , G06F13/42
CPC分类号： G06F13/4059
摘要： A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.
摘要翻译：双数据速率接口，其中针对数据相对于另一数据路径延迟数据路径的设置间隔进行扩展。数据被锁存到由中间循环型锁存器组成的寄存器中，例如L2 *锁存器。例如，如果延迟的一半数据在双倍数据速率周期的下半部分之前不可用，则数据的后半部分被允许具有围绕中间周期点的建立间隔，同时片内定时在建立之后，逻辑在时钟沿启动最少延迟的一半数据，而不用等待延迟数据的设置间隔的到期。

29. 发明申请

US20090217115A1 Method for Optimizing Scan Chains in an Integrated Circuit that has Multiple Levels of Hierarchy 有权
标题翻译：用于优化具有多层次结构的集成电路中的扫描链的方法
公开(公告)号：US20090217115A1
公开(公告)日：2009-08-27
申请号：US12035500
申请日：2008-02-22
申请人： Christopher J. Berry , Lawrence David Curley , Patrick James Meaney , Diana Lynn Orf
发明人： Christopher J. Berry , Lawrence David Curley , Patrick James Meaney , Diana Lynn Orf
IPC分类号： G01R31/3181
CPC分类号： G01R31/318536
摘要： A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned.
摘要翻译：一种用于优化集成电路中具有多层次层次结构的扫描链的方法，可以解决无限链和树桩，并分开所有其他链和树桩。通过将链包围的区域和残端的起始点和终点分成由多个网格框组成的网格，并且将网格框确定为网格框连接路由以访问所有网格框，来优化无限链和树桩的起始点和终点之间的网格框通过运行路由算法的计算机。优化的所有其他链和树桩被随机地分配给一个树桩，一个可以通过该树桩物理达到的链，并根据附加链中的锁存数，其物理位置和锁存数量向该残基添加一个附加链已分配

30. 发明申请

US20090210850A1 Method for Simplifying Tie Net Modeling for Router Performance 有权
标题翻译：简化路由器性能的网络建模方法
公开(公告)号：US20090210850A1
公开(公告)日：2009-08-20
申请号：US12032823
申请日：2008-02-18
申请人： Christopher J. Berry , Michael Alexander Bowen
发明人： Christopher J. Berry , Michael Alexander Bowen
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for preprocessing tie net routing data organizes the data into a plurality of tie nets each based on an optimal connection path between a pin or set of pins and the power grid. The router then routs the data embodying the thusly-simplified plurality of tie nets. Once the routing is complete, post processor takes the routed design and returns it to it's original net list state while keeping the routing solution.
摘要翻译：一种用于预处理联网网络路由数据的方法将数据组织成多个连接网络，每个连接网络基于引脚或引脚组与电网之间的最佳连接路径。然后，路由器路由体现由此简化的多个连接网络的数据。路由完成后，后处理器采用路由设计，并将其返回到原始网络列表状态，同时保持路由解决方案。

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