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21. 发明授权

US09385837B2 Cascaded viterbi bitstream generator 有权
标题翻译：级联维特比比特流发生器
公开(公告)号：US09385837B2
公开(公告)日：2016-07-05
申请号：US14380880
申请日：2013-01-18
申请人： LSI Corporation
发明人： Peter Kiss , Said E. Abdelli , Donald R. Laturell , James F. MacDonald , Ross S. Wilson
IPC分类号： H03M13/03 , H04L1/00 , G06F17/10 , H03M13/23 , H03M7/30 , H03M13/41
CPC分类号： H04L1/0059 , G06F17/10 , H03M7/3022 , H03M13/23 , H03M13/41
摘要： A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives an input signal and generates a first error signal indicative of a difference between the input signal and a first bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder which receives the first error signal and generates a second error signal indicative of a difference between the first error signal and a second bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the second bitstream generator stage. A third adder in the bitstream generator receives the first and second bitstream candidates and generates an output signal more closely approximating the input signal.
摘要翻译：比特流发生器至少包括以级联方式连接的第一和第二比特流发生器级。第一比特流发生器级包括第一加法器，其接收输入信号并产生第一误差信号，该第一误差信号指示输入信号和表示与由第一比特流产生的多个比特流候选中最接近输入信号的第一比特流候选之间的差异发电机阶段。第二比特流发生器级包括第二加法器，其接收第一误差信号并产生指示第一误差信号和第二比特流候选之间的差的第二误差信号，所述第二误码信号表示与由所述第一误差信号生成的多个比特流候选中最接近输入信号的近似值第二比特流发生器阶段。比特流发生器中的第三加法器接收第一和第二比特流候选，并产生更近似于输入信号的输出信号。

22. 发明授权

US09325356B2 Single-sideband transmitter using class-S amplifier 有权
标题翻译：单边带发射机采用S类放大器
公开(公告)号：US09325356B2
公开(公告)日：2016-04-26
申请号：US14380936
申请日：2013-03-15
申请人： LSI Corporation
发明人： Peter Kiss , Said E. Abdelli , Donald R. Laturell , James F. MacDonald , Steven C. Pinault , Ross S. Wilson
IPC分类号： H04B1/04 , H03C1/60 , H04B1/68 , H04L27/02 , H04L27/06
CPC分类号： H04B1/0475 , H03C1/52 , H03C1/60 , H03F3/24 , H04B1/68 , H04B2001/0408 , H04L27/02 , H04L27/06 , H04L27/063
摘要： An SSB transmitter includes a digital-to-digital converter generating first and second real signal components as a function of a complex input signal supplied to the transmitter, and a digital Hilbert transformation module coupled with the digital-to-digital converter and operative to generate first and second transformed signals as a function of the first and second real signal components. The transmitter further includes first and second bit-stream generators operative to generate first and second analog signals as a function of the first and second transformed signals, respectively. The transmitter includes first and second amplifiers. The first amplifier is operative to generate a first amplified signal as a function of the first analog signal. The second amplifier is operative to generate a second amplified signal as a function of the second analog signal. An analog hybrid coupler is connected with the first and second amplifiers and operative to perform an analog Hilbert transformation.
摘要翻译： SSB发射机包括数字 - 数字转换器，其产生作为提供给发射机的复合输入信号的函数的第一和第二实信号分量;以及数字希尔伯特变换模块，与数字 - 数字转换器耦合并且可操作以产生第一和第二变换信号作为第一和第二实信号分量的函数。发射机还包括第一和第二比特流发生器，用于分别产生作为第一和第二变换信号的函数的第一和第二模拟信号。发射机包括第一和第二放大器。第一放大器用于产生作为第一模拟信号的函数的第一放大信号。第二放大器用于产生作为第二模拟信号的函数的第二放大信号。模拟混合耦合器与第一和第二放大器连接并且可操作以执行模拟希尔伯特变换。

23. 发明申请

US20150074501A1 Cascaded Viterbi Bitstream Generator 有权
标题翻译：级联维特比比特流发生器
公开(公告)号：US20150074501A1
公开(公告)日：2015-03-12
申请号：US14380880
申请日：2013-01-18
申请人： LSI Corporation
发明人： Peter Kiss , Said E. Abdelli , Donald R. Laturell , James F. MacDonald , Ross S. Wilson
IPC分类号： H04L1/00 , H03M13/23 , G06F17/10
CPC分类号： H04L1/0059 , G06F17/10 , H03M7/3022 , H03M13/23 , H03M13/41
摘要： A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives an input signal and generates a first error signal indicative of a difference between the input signal and a first bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder which receives the first error signal and generates a second error signal indicative of a difference between the first error signal and a second bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the second bitstream generator stage. A third adder in the bitstream generator receives the first and second bitstream candidates and generates an output signal more closely approximating the input signal.
摘要翻译：比特流发生器至少包括以级联方式连接的第一和第二比特流发生器级。第一比特流发生器级包括第一加法器，其接收输入信号并产生第一误差信号，该第一误差信号指示输入信号和表示与由第一比特流产生的多个比特流候选中最接近输入信号的第一比特流候选之间的差异发电机阶段。第二比特流发生器级包括第二加法器，其接收第一误差信号并产生指示第一误差信号和第二比特流候选之间的差的第二误差信号，所述第二误码信号表示与由所述第一误差信号生成的多个比特流候选中最接近输入信号的近似值第二比特流发生器阶段。比特流发生器中的第三加法器接收第一和第二比特流候选，并产生更近似于输入信号的输出信号。

24. 发明授权

US08970406B2 Interleaved multipath digital power amplification 有权
标题翻译：交错多路数字功率放大
公开(公告)号：US08970406B2
公开(公告)日：2015-03-03
申请号：US14184334
申请日：2014-02-19
申请人： LSI Corporation
发明人： Peter Kiss , Said E. Abdelli , Donald R. Laturell , Ross S. Wilson , James F. MacDonald
IPC分类号： H03M9/00 , H04L25/02 , H03M3/00 , H03F3/217 , H03H17/00 , H03H17/02 , H04L27/02
CPC分类号： H03M9/00 , H03F3/217 , H03F2200/331 , H03H17/0018 , H03H17/0273 , H03H17/028 , H03M3/30 , H03M3/37 , H03M3/47 , H04L25/02 , H04L27/02
摘要： In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.
摘要翻译：在一个实施例中，射频发射机的功率放大系统包括数字信号源，该数字信号源向交错位流发生器提供数字输入信号，该数字信号源向切换功率放大器输出数字切换信号。交错比特流发生器具有八路交织体系结构，有助于降低交错比特流发生器的有效时钟速率要求。交错比特流生成器包括用于接收数字输入信号并将八个分数延迟的数字输出信号输出到比特流生成阵列的分数延迟滤波器阵列，适用于将八个对应的比特流输出到串行化器块，将八个比特流组合成数字切换信号。可以调整交错信号的相对相位以实现某些期望的效果。

25. 发明申请

US20140269978A1 INTERLEAVED MULTIPATH DIGITAL POWER AMPLIFICATION 审中-公开
标题翻译：交互式多路数字功率放大
公开(公告)号：US20140269978A1
公开(公告)日：2014-09-18
申请号：US14184323
申请日：2014-02-19
申请人： LSI CORPORATION
发明人： Peter Kiss , Said E. Abdelli , Donald R. Laturell , Ross S. Wilson , James F. MacDonald
IPC分类号： H04L25/02
CPC分类号： H03M9/00 , H03F3/217 , H03F2200/331 , H03H17/0018 , H03H17/0273 , H03H17/028 , H03M3/30 , H03M3/37 , H03M3/47 , H04L25/02 , H04L27/02
摘要： In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.
摘要翻译：在一个实施例中，射频发射机的功率放大系统包括数字信号源，该数字信号源向交错位流发生器提供数字输入信号，该数字信号源向切换功率放大器输出数字切换信号。交错比特流发生器具有八路交织体系结构，有助于降低交错比特流发生器的有效时钟速率要求。交错比特流生成器包括用于接收数字输入信号并将八个分数延迟的数字输出信号输出到比特流生成阵列的分数延迟滤波器阵列，适用于将八个对应的比特流输出到串行化器块，将八个比特流组合成数字切换信号。可以调整交错信号的相对相位以实现某些期望的效果。

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