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1. 发明授权

US08015225B2 Multi-step non-linear time-discrete processing 有权
标题翻译：多步非线性时间离散处理
公开(公告)号：US08015225B2
公开(公告)日：2011-09-06
申请号：US11722260
申请日：2004-12-21
申请人： Lars Richard Birger Hellberg
发明人： Lars Richard Birger Hellberg
IPC分类号： G06F17/10
CPC分类号： H03H17/0261 , H03H17/0018 , H03H17/06 , H03H2218/12
摘要： A non-linear processing device (1) is presented, in which fractional-delay filtering (20)—fractional as compared with a sample rate used in the processing steps—is used between successive processing steps (10). A corresponding method is also presented. The fractional delay (20) exposes the signal in-between the original samples to the non-linear processing (30, 40). A lower sample rate or a higher signal quality can thus be achieved. The so-called fractional sample delays are preferably chosen differently for different systems depending on bandwidths, number of channels, number of non-linear processing steps (10) and other varying factors. The multi-step non-linear processing (10) concept of the invention is preferably used within a cascade of non-linear modifications and/or filtering steps (10).
摘要翻译：提出了一种非线性处理装置（1），其中在连续的处理步骤（10）之间使用其中与在处理步骤中使用的采样率相比的分数延迟滤波（20） - 分数。还提出了相应的方法。分数延迟（20）将原始样本之间的信号暴露于非线性处理（30,40）。因此可以实现更低的采样率或更高的信号质量。根据带宽，通道数，非线性处理步骤（10）的数量和其他变化因素，优选地针对不同系统不同地选择所谓的分数采样延迟。本发明的多步非线性处理（10）概念优选地在级联的非线性修改和/或过滤步骤（10）中使用。

2. 发明申请

US20140266820A1 INTERLEAVED MULTIPATH DIGITAL POWER AMPLIFICATION 有权
公开(公告)号：US20140266820A1
公开(公告)日：2014-09-18
申请号：US14184334
申请日：2014-02-19
申请人： LSI Corporation
发明人： Peter Kiss , Said E. Abdelli , Donald R. Laturell , Ross S. Wilson , James F. MacDonald
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03F3/217 , H03F2200/331 , H03H17/0018 , H03H17/0273 , H03H17/028 , H03M3/30 , H03M3/37 , H03M3/47 , H04L25/02 , H04L27/02
摘要： In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.

3. 发明申请

US20180167056A1 APPARATUSES AND METHODS FOR SHIFTING A DIGITAL SIGNAL BY A SHIFT TIME TO PROVIDE A SHIFTED SIGNAL 审中-公开
公开(公告)号：US20180167056A1
公开(公告)日：2018-06-14
申请号：US15811851
申请日：2016-06-08
申请人： Intel IP Corporation
发明人： Thomas Bauernfeind , Andreas Menkhoff , Michael Bruennert
IPC分类号： H03H17/02 , H03H17/00 , H03H17/06
CPC分类号： H03H17/0291 , H03F2200/336 , H03H17/0018 , H03H17/0635
摘要： An apparatus for shifting a digital signal having a first sample rate by a shift time to provide a shifted signal having a second sample rate is provided. The apparatus includes a sample rate converter configured to provide a value of an interpolated signal at a compensated sample time as a sample of the shifted signal, the interpolated signal being based on the digital signal. The sample rate converter is configured to modify a time interval between a sample time of the digital signal and the compensated sample time based on the shift time.

4. 发明授权

US08664994B1 System to generate a predetermined fractional period time delay 有权
$System to generate a predetermined fractional period time delay$
标题翻译：系统以产生预定的分数周期时间延迟
公开(公告)号：US08664994B1
公开(公告)日：2014-03-04
申请号：US13790002
申请日：2013-03-08
申请人： Department of Electronics and Information Technology , Indian Institute of Science
发明人： Bharadwaj Amrutur , Pratap Kumar Das
IPC分类号： H03H11/26
CPC分类号： H03H17/0018
摘要： Embodiments of the disclosure relate to an all-digital technique for generating an accurate delay irrespective of the inaccuracies of a controllable delay line. A sub-sampling technique based delay measurement unit capable of measuring delays accurately for the full period range is used as the feedback element to build accurate fractional period delays based on input digital control bits. The delay generation system periodically measures and corrects the error and maintains it at the minimum value without requiring any special calibration phase. A significant improvement in accuracy is obtained for a commercial programmable delay generator chip. The time-precision trade-off feature of the delay measurement unit is utilized to reduce the locking time. Loop dynamics are adjusted to stabilize the delay after the minimum error is achieved, thus avoiding additional jitter.
摘要翻译：本公开的实施例涉及用于产生精确延迟的全数字技术，而不管可控延迟线的不准确性。使用能够在全周期范围内精确测量延迟的基于子采样技术的延迟测量单元作为反馈元件，以基于输入数字控制位建立精确的分数周期延迟。延迟生成系统周期性地测量和纠正误差并将其维持在最小值，而不需要任何特殊的校准阶段。商业可编程延迟发生器芯片获得了精度的显着提高。延迟测量单元的时间精度权衡特征被用来减少锁定时间。调整环路动力学以在实现最小误差之后稳定延迟，从而避免额外的抖动。

5. 发明申请

US20170064651A1 SYNCHRONIZATION OF AUDIO STREAMS AND SAMPLING RATE FOR WIRELESS COMMUNICATION 审中-公开
标题翻译：音频流的同步和无线通信采样率
公开(公告)号：US20170064651A1
公开(公告)日：2017-03-02
申请号：US15248287
申请日：2016-08-26
申请人： Alex Volkov , Baktash Boghrati , Edward John Cunningham , Mohammad Reza Movahedi , Jeffrey Paul Solum
发明人： Alex Volkov , Baktash Boghrati , Edward John Cunningham , Mohammad Reza Movahedi , Jeffrey Paul Solum
IPC分类号： H04W56/00 , H04R25/00
CPC分类号： H04W56/001 , G10H1/0083 , G10H2240/325 , G10H2250/631 , H03H17/0018 , H03H17/0642 , H04L2012/5681 , H04R25/552 , H04R25/554 , H04R2225/55 , H04W56/004
摘要： Disclosed herein, among other things, are methods and apparatus for providing a time-stamp based controller for synchronization of sink or source sampling rate with external packet rate. A method for wireless communications includes receiving a transmission of a packet using a wireless transceiver of an electronic device, and using a processor of the electronic device to read a first value of a system timer and store the first value as an arrival time-stamp. The packet is decoded and processed by the processor, and sent to an output. When the processed packet is sent, a second value of the system timer is read, adjusted and stored as a departure time-stamp. The arrival time-stamp and the departure time-stamp are used to calculate an adjustment stimulus for a sample rate actuator of the electronic device. The sample rate actuator is configured to maintain synchronization of sampling rate with an external packet rate.
摘要翻译：这里公开的是用于提供基于时间戳的控制器的方法和装置，用于使宿或源采样率与外部分组速率同步。一种用于无线通信的方法包括使用电子设备的无线收发器接收分组的传输，并且使用所述电子设备的处理器来读取系统定时器的第一值并存储所述第一值作为到达时间戳。数据包被处理器解码和处理，并发送到输出。当处理的数据包被发送时，读取，调整和存储系统定时器的第二个值作为出发时间戳。使用到达时间戳和出发时间戳来计算电子设备的采样率致动器的调整刺激。采样率致动器被配置为保持采样率与外部分组速率的同步。

6. 发明申请

US20090176466A1 Apparatuses and a Method for Reducing Peak Power in a Transmitter of Telecommunications Systems 审中-公开
标题翻译：电信系统发射机降低峰值功率的装置和方法
公开(公告)号：US20090176466A1
公开(公告)日：2009-07-09
申请号：US12373316
申请日：2006-07-11
申请人： Richard Hellberg , Torbjorn Widhe
发明人： Richard Hellberg , Torbjorn Widhe
IPC分类号： H04B1/04
CPC分类号： H04L27/2614 , H03H17/0018
摘要： The present invention relates to an apparatus (100) for reducing peak power in a transmitter for use in telecommunications systems. The invention also relates to a method for reducing peak power in a transmitter for use in telecommunications system and to a base station (500) including such an apparatus. An apparatus according to the invention includes successive processing stages (10); where each stage (10) has an input main signal (1). Each stage of said apparatus further includes a peak finder means (11) arranged to find at least one peak of said input main signal (1) based on a predetermined threshold level; a manipulation means (12) arranged to generate a scaled, rotated and shifted kernel signal (2) based on information on at least one peak of said input main signal (1); a combiner (13) arranged to subtract the scaled rotated and shifted kernel signal (2) from a delayed version of the input signal (1) generating thereof an output signal (4) having reduced peak or peaks; and said apparatus further characterized in that it comprises a fractional sample shifting means (20) arranged to apply a sample shifting on the output signal (4) from at least one of said successive processing stages (10).
摘要翻译：本发明涉及一种用于减少在电信系统中使用的发射机中的峰值功率的装置（100）。本发明还涉及用于减少在电信系统中使用的发射机中的峰值功率和包括这种装置的基站（500）的方法。根据本发明的装置包括连续的处理阶段（10）; 其中每个级（10）具有输入主信号（1）。所述装置的每一级还包括一个峰值寻找器装置（11），用于基于预定的阈值电平找到所述输入主信号（1）的至少一个峰值; 基于关于所述输入主信号（1）的至少一个峰值的信息，布置成产生缩放的，旋转和移位的内核信号（2）的操纵装置（12）。组合器（13），被布置成从输入信号（1）的延迟版本中减去经缩放的旋转和移位的内核信号（2），产生具有降低的峰值或峰值的输出信号（4）并且所述装置进一步的特征在于，其包括分数采样移位装置（20），其布置成从所述连续处理级（10）中的至少一个对输出信号（4）施加样本移位。

7. 发明申请

US20170338803A1 Filter for a Brushless DC Motor 审中-公开
公开(公告)号：US20170338803A1
公开(公告)日：2017-11-23
申请号：US15600005
申请日：2017-05-19
申请人： Ultra Electronics Limited
发明人： Andrew Ceri Davis
IPC分类号： H03H17/02 , H02P6/15 , H03H17/00 , H02P7/03
CPC分类号： H03H17/0294 , H02P6/153 , H02P6/18 , H02P7/05 , H03H17/0018 , H03H2017/0297
摘要： A filter for use with a brushless DC motor to filter a signal received from a floating terminal of the brushless DC motor, wherein the filter is configured such that a time delay introduced by the filter to the signal received from the floating terminal is equal to the time taken for a rotor of the motor to rotate through an angle equal to half of a commutation step of the motor.

8. 发明授权

US08970406B2 Interleaved multipath digital power amplification 有权
标题翻译：交错多路数字功率放大
公开(公告)号：US08970406B2
公开(公告)日：2015-03-03
申请号：US14184334
申请日：2014-02-19
申请人： LSI Corporation
发明人： Peter Kiss , Said E. Abdelli , Donald R. Laturell , Ross S. Wilson , James F. MacDonald
IPC分类号： H03M9/00 , H04L25/02 , H03M3/00 , H03F3/217 , H03H17/00 , H03H17/02 , H04L27/02
CPC分类号： H03M9/00 , H03F3/217 , H03F2200/331 , H03H17/0018 , H03H17/0273 , H03H17/028 , H03M3/30 , H03M3/37 , H03M3/47 , H04L25/02 , H04L27/02
摘要： In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.
摘要翻译：在一个实施例中，射频发射机的功率放大系统包括数字信号源，该数字信号源向交错位流发生器提供数字输入信号，该数字信号源向切换功率放大器输出数字切换信号。交错比特流发生器具有八路交织体系结构，有助于降低交错比特流发生器的有效时钟速率要求。交错比特流生成器包括用于接收数字输入信号并将八个分数延迟的数字输出信号输出到比特流生成阵列的分数延迟滤波器阵列，适用于将八个对应的比特流输出到串行化器块，将八个比特流组合成数字切换信号。可以调整交错信号的相对相位以实现某些期望的效果。

9. 发明申请

US20140269978A1 INTERLEAVED MULTIPATH DIGITAL POWER AMPLIFICATION 审中-公开
标题翻译：交互式多路数字功率放大
公开(公告)号：US20140269978A1
公开(公告)日：2014-09-18
申请号：US14184323
申请日：2014-02-19
申请人： LSI CORPORATION
发明人： Peter Kiss , Said E. Abdelli , Donald R. Laturell , Ross S. Wilson , James F. MacDonald
IPC分类号： H04L25/02
CPC分类号： H03M9/00 , H03F3/217 , H03F2200/331 , H03H17/0018 , H03H17/0273 , H03H17/028 , H03M3/30 , H03M3/37 , H03M3/47 , H04L25/02 , H04L27/02
摘要： In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.
摘要翻译：在一个实施例中，射频发射机的功率放大系统包括数字信号源，该数字信号源向交错位流发生器提供数字输入信号，该数字信号源向切换功率放大器输出数字切换信号。交错比特流发生器具有八路交织体系结构，有助于降低交错比特流发生器的有效时钟速率要求。交错比特流生成器包括用于接收数字输入信号并将八个分数延迟的数字输出信号输出到比特流生成阵列的分数延迟滤波器阵列，适用于将八个对应的比特流输出到串行化器块，将八个比特流组合成数字切换信号。可以调整交错信号的相对相位以实现某些期望的效果。

10. 发明申请

US20080133183A1 Multi-Step Non-Linear Time-Discrete Processing 有权
标题翻译：多步非线性时间离散处理
公开(公告)号：US20080133183A1
公开(公告)日：2008-06-05
申请号：US11722260
申请日：2004-12-21
申请人： Richard Hellberg
发明人： Richard Hellberg
IPC分类号： G06F15/00 , H03F1/00
CPC分类号： H03H17/0261 , H03H17/0018 , H03H17/06 , H03H2218/12
摘要： A non-linear processing device (1) is presented, in which fractional-delay filtering (20)—fractional as compared with a sample rate used in the processing steps—is used between successive processing steps (10). A corresponding method is also presented. The fractional delay (20) exposes the signal in-between the original samples to the non-linear processing (30, 40). A lower sample rate or a higher signal quality can thus be achieved. The so-called fractional sample delays are preferably chosen differently for different systems depending on bandwidths, number of channels, number of non-linear processing steps (10) and other varying factors. The multi-step non-linear processing (10) concept of the invention is preferably used within a cascade of non-linear modifications and/or filtering steps (10).
摘要翻译：提出了一种非线性处理装置（1），其中在连续的处理步骤（10）之间使用其中与在处理步骤中使用的采样率相比的分数延迟滤波（20） - 分数。还提出了相应的方法。分数延迟（20）将原始样本之间的信号暴露于非线性处理（30,40）。因此可以实现更低的采样率或更高的信号质量。根据带宽，通道数，非线性处理步骤（10）的数量和其他变化因素，优选地针对不同系统不同地选择所谓的分数采样延迟。本发明的多步非线性处理（10）概念优选地在级联的非线性修改和/或过滤步骤（10）中使用。

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