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31. 发明申请

US20080231319A1 DEDICATED INPUT/OUTPUT FIRST IN/FIRST OUT MODULE FOR A FIELD PROGRAMMABLE GATE ARRAY 审中-公开
标题翻译：用于现场可编程门阵列的专用输入/输出第一个/第一个输出模块
公开(公告)号：US20080231319A1
公开(公告)日：2008-09-25
申请号：US12131722
申请日：2008-06-02
申请人： William C. Plants , Arunangshu Kundu
发明人： William C. Plants , Arunangshu Kundu
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17744
摘要： A field programmable gate array architecture having a plurality of input/output pads. The architecture comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; an input/output block controller programmably coupled to the plurality of dedicated input/output first-in/first-out memory blocks; and a routing interconnect architecture programmably coupling the logic clusters, input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/output buffers and the input/output clusters.
摘要翻译：具有多个输入/输出焊盘的现场可编程门阵列架构。该架构包括：多个逻辑簇; 多个输入/输出群集; 多个输入/输出缓冲器; 多个专用输入/输出先进先出存储块，专用输入/输出先进先出存储块具有耦合到多个输入/输出存储器中的一个的先进先出存储器，输出垫; 可编程地耦合到所述多个专用输入/输出先入/先出存储块的输入/输出块控制器; 以及可编程地耦合逻辑簇，输入/输出缓冲器和输入/输出群集的路由互连结构，其中专用输入/输出先入先出存储块可编程地耦合在输入/输出缓冲器与输入/ 输出集群。

32. 发明申请

US20080204074A1 DEDICATED INTERFACE ARCHITECTURE FOR A HYBRID INTEGRATED CIRCUIT 有权
标题翻译：用于混合集成电路的专用接口架构
公开(公告)号：US20080204074A1
公开(公告)日：2008-08-28
申请号：US12114143
申请日：2008-05-02
申请人： King W. Chan , William C.T. Shu , Sinan Kaptanoglu , Chi Fung Cheng
发明人： King W. Chan , William C.T. Shu , Sinan Kaptanoglu , Chi Fung Cheng
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , G06F15/7867
摘要： An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.
摘要翻译：用于混合IC的接口设计，其利用专用接口轨道来允许信号与FPGA部分的逻辑块分布地接口，从而提供混合IC的FPGA和ASIC部分之间的更快更有效的通信。

33. 发明申请

US20080197878A1 ENHANCED FIELD PROGRAMMABLE GATE ARRAY 失效
标题翻译：增强现场可编程门阵列
公开(公告)号：US20080197878A1
公开(公告)日：2008-08-21
申请号：US12111660
申请日：2008-04-29
申请人： Samuel W. Beal , Sinan Kaptonoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
发明人： Samuel W. Beal , Sinan Kaptonoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
IPC分类号： H03K19/173
CPC分类号： H03K19/17768 , H03K19/1736 , H03K19/17704 , H03K19/17732 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
摘要翻译：增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

34. 发明申请

US20080197450A1 AMORPHOUS CARBON METAL-TO-METAL ANTIFUSE WITH ADHESION PROMOTING LAYERS 审中-公开
标题翻译：非粘性金属对金属抗粘附剂与粘合促进层
公开(公告)号：US20080197450A1
公开(公告)日：2008-08-21
申请号：US12103550
申请日：2008-04-15
申请人： Frank W. Hawley , A. Farid Issaq , John L. McCollum , Shubhra M. Gangopadhyay , Jorge A. Lubguban , Jin Miao Shen
发明人： Frank W. Hawley , A. Farid Issaq , John L. McCollum , Shubhra M. Gangopadhyay , Jorge A. Lubguban , Jin Miao Shen
IPC分类号： H01L23/525
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , Y10S257/903 , H01L2924/00
摘要： A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising SixCy and SixNy. The ratio of x to y in SixCy is in a range of about 1±0.4, and the ratio of x to y in SixNy is in a range of about 0.75±0.225.
摘要翻译：具有下金属电极的金属对金属反熔丝，设置在下金属电极上的下薄增粘层，设置在薄粘附促进层上的无定形碳反应熔剂层，设置在所述反熔丝之上的上薄增粘层材料层和上部金属电极。薄粘附促进层的厚度约为2埃至20埃，并且来自选自包含Si x Si x Si和Si x的组的材料， / SUB> Y 。 Si x Si x y中的x与y的比率在约1±0.4的范围内，并且Si x x y中的x与y的比例， SUB> N 在约0.75±0.225的范围内。

35. 发明申请

US20080191740A1 CLOCK TREE NETWORK IN A FIELD PROGRAMMABLE GATE ARRAY 有权
标题翻译：时钟树网络在现场可编程门阵列中
公开(公告)号：US20080191740A1
公开(公告)日：2008-08-14
申请号：US12105524
申请日：2008-04-18
申请人： Arunangshu Kundu
发明人： Arunangshu Kundu
IPC分类号： H03K19/177 , H03L7/06
CPC分类号： H03K19/1774 , G06F1/10
摘要： A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array with programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network selects a signal from a clock signal from the interface or a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.
摘要翻译：用于现场可编程门阵列的时钟树分配网络包括具有从外部时钟信号，内部时钟信号，多个锁相环单元输出信号和可编程元件中的至少一个选择的根信号的接口。 FPGA包括具有将逻辑阵列耦合到可编程路由架构和接口的可编程元件的逻辑阵列。路由时钟网络从来自接口的时钟信号，来自逻辑阵列的本地信号通过路由架构Vcc或接地选择信号，并且通过时钟树分配网络将所选择的信号路由到逻辑阵列。硬连线时钟网络从来自接口的时钟信号或来自路由架构的本地信号中选择信号，并且通过时钟树分配网络将所选择的信号路由到逻辑阵列中的多个触发器。

36. 发明授权

US07400283B1 Mixed signal system-on-a-chip integrated simultaneous multiple sample/hold circuits and embedded analog comparators 有权
标题翻译：混合信号片上集成同时多个采样/保持电路和嵌入式模拟比较器
公开(公告)号：US07400283B1
公开(公告)日：2008-07-15
申请号：US11612771
申请日：2006-12-19
申请人： Limin Zhu
发明人： Limin Zhu
IPC分类号： H03M1/00
CPC分类号： H03M1/1225
摘要： An integrated circuit includes a plurality of circuit groups, each circuit group containing a plurality of analog inputs, a buffer, a sample/hold circuit and a comparator. Each buffer has an input to which any of the analog inputs in its group may be programmably connected. The output of each buffer is coupled to the input of the sample/hold circuit in the group. The output of each sample/hold circuit is coupled to one input of a multiplexer. The output of the multiplexer is coupled to the input of an amplifier having programmable gain and programmable offset. The comparator in each group has inputs that may be programmably coupled to at least one analog input in the group or to a reference voltage source.
摘要翻译：集成电路包括多个电路组，每个电路组包含多个模拟输入，缓冲器，采样/保持电路和比较器。每个缓冲器具有其组中的任何模拟输入可以可编程地连接到的输入。每个缓冲器的输出耦合到组中的采样/保持电路的输入。每个采样/保持电路的输出耦合到多路复用器的一个输入端。多路复用器的输出耦合到具有可编程增益和可编程偏移的放大器的输入。每组中的比较器具有可编程地耦合到组中的至少一个模拟输入或参考电压源的输入。

37. 发明授权

US07394286B2 Field programmable gate array long line routing network 有权
标题翻译：现场可编程门阵列长线路由网络
公开(公告)号：US07394286B2
公开(公告)日：2008-07-01
申请号：US11692717
申请日：2007-03-28
申请人： Volker Hecht
发明人： Volker Hecht
IPC分类号： H03K19/173
CPC分类号： H03K19/17736
摘要： A multi-directional routing repeater has a plurality of buffers, each of the plurality of buffers has an input and an output. The output of each of the plurality of buffers is connected to a separate routing line for transmitting a signal in a separate direction of a first set of routing lines, and the input of each of the plurality of buffers is connected to one of a first set of programmable switches, one of a second set of programmable switches, one of a third set of programmable switches, and one of a fourth set of programmable switches, and each one of the first set of programmable switches is connected to a separate one of the second set of programmable switches and a separate one of the second set of programmable switches, none of which are connected to an input of a same one of the plurality of buffers. Each one of the first set of programmable switches is connected to a separate routing line for transmitting a signal in a separate direction of a second set of routing lines.
摘要翻译：多方向路由中继器具有多个缓冲器，多个缓冲器中的每一个具有输入和输出。多个缓冲器中的每一个的输出被连接到单独的路由线路，用于在第一组路由线路的单独方向上发送信号，并且多个缓冲器中的每一个的输入连接到第一组的可编程开关，第二组可编程开关之一，第三组可编程开关之一和第四组可编程开关之一，并且第一组可编程开关中的每一个连接到第二组可编程开关和第二组可编程开关中的单独一个，其中没有一个连接到多个缓冲器中的相同的一个缓冲器的输入端。第一组可编程开关中的每一个连接到用于在第二组路由线的单独方向上发送信号的分离的路线。

38. 发明授权

US07393722B1 Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material 失效
标题翻译：可重复编程的金属 - 金属反熔丝采用含碳反熔体材料
公开(公告)号：US07393722B1
公开(公告)日：2008-07-01
申请号：US11195002
申请日：2005-08-01
申请人： A. Farid Issaq , Frank Hawley , John McCollum
发明人： A. Farid Issaq , Frank Hawley , John McCollum
IPC分类号： H01L21/82
CPC分类号： H01L23/5252 , G11C17/16 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer.
摘要翻译：在集成电路中的两个金属互连层之间设置可再编程的金属对金属反熔丝。由Ti形成下阻挡层。下部粘附促进层设置在下部Ti阻挡层上。选自包含至少一种无定形碳和掺杂有氢和氟中的至少一种的无定形碳的反熔丝材料层设置在下部粘附促进层上。上部粘合促进层设置在反熔丝材料层上。在上部粘合促进层上设置上部Ti阻挡层。

39. 发明申请

US20080136446A1 BLOCK LEVEL ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY 失效
标题翻译：在现场可编程门阵列中的块级路由架构
公开(公告)号：US20080136446A1
公开(公告)日：2008-06-12
申请号：US12034555
申请日：2008-02-20
申请人： Sinan Kaptanoglu
发明人： Sinan Kaptanoglu
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H01L27/11803
摘要： An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of the B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy is are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors. Each BC routing channel is coupled to an expressway tab to provide access for each B1 block to the expressway routing channels M1, M2, and M3, respectively. Each BC routing channel has nine interconnect conductors which are grouped into three groups of three interconnect conductors. Each group of three interconnect conductors is connected to a first side of a Extension Board (EB) 3×3 switch matrix. A second side of each EB 3×3 switch matrix is coupled to the E-tab. Between adjacent B1 blocks, in both the horizontal and vertical directions, the leads on the second side of a first EB 3×3 switch matrix may be coupled to the leads on the second side of second EB3×3 switch matrix by BC criss-cross extension.
摘要翻译： FPGA架构具有顶级，中级和低级。该体系结构的顶层是排列成矩形阵列并由外围的I / O块包围的B16x16瓦数组。在B16x16瓦片的四面中，每个I / O块也与高速公路路由通道相关联。中层层次的B16x16瓦片是16块16块阵列。中层层次中的路由资源是包括互连导体组的高速公路路由信道M 1，M 2和M 3。在半层次FPGA架构的最底层，有块连接（BC）路由通道，局域网（LM）路由通道和直接连接（DC）互连导线。每个BC路由信道被耦合到高速公路标签，以分别向高速公路路由信道M 1，M 2和M 3提供每个B1块的接入。每个BC路由信道具有九个互连导体，它们分成三组三个互连导体。每组三个互连导体连接到扩展板（EB）3x3开关矩阵的第一侧。每个EB 3x3开关矩阵的第二面耦合到E-tab。在相邻B1块之间，在水平和垂直方向上，第一EB 3×3开关矩阵的第二侧上的引线可以通过BC交叉扩展耦合到第二EB3×3开关矩阵的第二侧上的引线。

40. 发明授权

US07385421B2 Block symmetrization in a field programmable gate array 有权
标题翻译：在现场可编程门阵列中的块对称
公开(公告)号：US07385421B2
公开(公告)日：2008-06-10
申请号：US11748865
申请日：2007-05-15
申请人： Sinan Kaptanoglu
发明人： Sinan Kaptanoglu
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728 , H03K19/1778 , H03K19/17796
摘要： An FPGA architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing channels, and direct connect interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the clusters includes first and second LUT3s, a LUT2, and a DFF. Each of the LUT3s have three inputs and one output. Each of the LUT2s have two inputs and one output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are multiplexed to the input of DFF, and symmetrized with the output of the DFF to form two outputs of each of the clusters.
摘要翻译： FPGA架构具有顶级，中级和低级。顶级是由I / O块包围的B16x16瓦数组。中间路由资源是高速公路路由信道，包括互连导体。在最底层，有块连接路由通道，本地网状路由通道和直接连接互连导体，以将逻辑元件连接到更多的路由资源。每个B 1块包括四组设备。每个簇包括第一和第二LUT 3 s，LUT 2和DFF。 LUT 3中的每一个具有三个输入和一个输出。 LUT 2中的每一个具有两个输入和一个输出。每个DFF都有数据输入和数据输出。在每个簇中，LUT 3的输出被复用到DFF的输入，并且与DFF的输出对称，以形成每个簇的两个输出。

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