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41. 发明授权

US08138758B2 Method of controlling a magnetoresistive device using an electric field pulse 有权
标题翻译：使用电场脉冲控制磁阻器件的方法
公开(公告)号：US08138758B2
公开(公告)日：2012-03-20
申请号：US12050208
申请日：2008-03-18
申请人： Joerg Wunderlich , Tomas Jungwirth , Jan Zemen , Bryan Gallagher , Claude Chappert , Thibaut Devolder
发明人： Joerg Wunderlich , Tomas Jungwirth , Jan Zemen , Bryan Gallagher , Claude Chappert , Thibaut Devolder
IPC分类号： G01R33/02 , G11C11/02
CPC分类号： G01R33/093 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/5607 , H01L43/08
摘要： A method of operating a magnetoresistive device is described. The device comprises a ferromagnetic region configured to exhibit magnetic anisotropy and to allow magnetisation thereof to be switched between at least first and second orientations and a gate capacitively coupled to the ferromagnetic region. The method comprises applying an electric field pulse to the ferromagnetic region so as to cause orientation of magnetic anisotropy to change for switching magnetisation between the first and second orientations.
摘要翻译：描述了操作磁阻器件的方法。该器件包括铁磁区域，其被配置为表现出磁各向异性并允许其磁化在至少第一和第二取向之间切换，并且栅极电容耦合到铁磁区域。该方法包括将电场脉冲施加到铁磁区域，以使磁各向异性的取向发生变化，以便在第一和第二取向之间切换磁化。

42. 发明申请

US20110128778A1 Predictive Thermal Preconditioning and Timing Control for Non-Volatile Memory Cells 有权
标题翻译：非易失性记忆体的预测热预处理和时序控制
公开(公告)号：US20110128778A1
公开(公告)日：2011-06-02
申请号：US13016390
申请日：2011-01-28
申请人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
发明人： Yiran Chen , Hai Li , Harry Hongyue Liu , Dimitar V. Dimitrov , Alan Xuguang Wang , Xiaobin Wang
IPC分类号： G11C11/02 , G11C7/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.
摘要翻译：一种使用热预处理来将数据写入诸如自旋转矩传递随机存取存储器（STRAM）存储器单元的非易失性存储单元的方法和装置。在一些实施例中，将逻辑状态写入与第一块地址相关联的无条件非易失性第一存储器单元。热预处理同时应用于与响应于第一块地址选择的第二块地址相关联的非易失性第二存储器单元。

43. 发明授权

US07902579B2 Magnetic memory devices using magnetic domain dragging 有权
标题翻译：使用磁畴拖曳的磁存储器件
公开(公告)号：US07902579B2
公开(公告)日：2011-03-08
申请号：US11505969
申请日：2006-08-18
申请人： Chee-kheng Lim , Eun-sik Kim , Yong-su Kim
发明人： Chee-kheng Lim , Eun-sik Kim , Yong-su Kim
IPC分类号： G11C11/02
CPC分类号： G11C11/15 , G11C11/5607 , G11C19/0808 , H01L27/228
摘要： A magnetic memory device includes a memory region, an input and a sensor. The memory region includes a free layer, a pinned layer and a non-magnetic layer. The free layer has adjacent sectors and a magnetic domain wall. The pinned layer corresponds to the sectors and has a fixed magnetization direction. The non-magnetic layer is formed between the free layer and the pinned layer. The memory region includes a magnetic domain wall stopper for stopping the magnetic domain wall formed at each boundary of the sectors. The input is electrically connected to one end of the free layer for inputting a signal for magnetic domain dragging. The sensor measures a current flowing through the memory region.
摘要翻译：磁存储器件包括存储区域，输入端和传感器。存储区包括自由层，钉扎层和非磁性层。自由层具有相邻扇区和磁畴壁。被钉扎层对应于扇区并且具有固定的磁化方向。非磁性层形成在自由层和被钉扎层之间。存储区域包括用于停止形成在扇区的每个边界处的磁畴壁的磁畴壁塞。输入电连接到自由层的一端，用于输入用于磁畴拖动的信号。传感器测量流过存储器区域的电流。

44. 发明授权

US07888755B2 Magnetic storage device with intermediate layers having different sheet resistivities 有权
标题翻译：具有中间层具有不同片电阻率的磁存储装置
公开(公告)号：US07888755B2
公开(公告)日：2011-02-15
申请号：US11235384
申请日：2005-09-26
申请人： Masanori Hosomi , Kazuhiro Ohba , Hiroshi Kano , Yiming Huai , Zhitao Diao , Mahendra Pakala
发明人： Masanori Hosomi , Kazuhiro Ohba , Hiroshi Kano , Yiming Huai , Zhitao Diao , Mahendra Pakala
IPC分类号： H01L29/82 , G11C11/02
CPC分类号： G11C11/16
摘要： A storage element 3 has an arrangement in which magnetization fixed layers 31 and 32 are provided above and below a storage layer 17 for storing information based on the magnetization state of a magnetic material through intermediate layers 16 and 18, directions of magnetizations M15 and M19 of ferromagnetic layers 15 and 19 closest to the storage layer 17 of the magnetization fixed layers 31 and 32 above and below the storage layer 17 are opposite to each other, the two intermediate layers 16 and 18 above and below the storage layer 17 have a significant difference between sheet resistivity values thereof and in which the direction of a magnetization M1 of the storage layer 17 is changed with application of an electric current to the lamination layer direction to record information on the storage layer 17.
摘要翻译：存储元件3具有这样的配置，其中磁化固定层31和32设置在存储层17的上方和下方，用于基于通过中间层16和18的磁性材料的磁化状态来存储信息，磁化M15和M19的方向最靠近存储层17上方和下方的磁化固定层31和32的存储层17的铁磁层15和19彼此相对，存储层17上方和下方的两个中间层16和18具有显着差异在其电阻率值之间，并且其中存储层17的磁化M1的方向随施加到层压层方向的电流而改变以在存储层17上记录信息。

45. 发明授权

US07885097B2 Non-volatile memory array with resistive sense element block erase and uni-directional write 有权
标题翻译：具有电阻感测元件块擦除和单向写入的非易失性存储器阵列
公开(公告)号：US07885097B2
公开(公告)日：2011-02-08
申请号：US12501077
申请日：2009-07-10
申请人： Daniel S. Reed , Yong Lu , Andrew John Carter , Hai Li
发明人： Daniel S. Reed , Yong Lu , Andrew John Carter , Hai Li
IPC分类号： G11C7/12 , G11C8/12 , G11C11/16 , G11C11/02 , G11C11/14
CPC分类号： G11C13/0097 , G11C11/1659 , G11C11/1675 , G11C13/0004 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C2013/009 , G11C2213/76
摘要： In accordance with various embodiments, a column of non-volatile memory cells is connected between opposing first and second control lines. A fixed reference voltage is applied to the second control line. The memory cells are simultaneously programmed to a first resistive state by applying a first voltage to the first control line that is greater than the fixed reference voltage. Less than all of the memory cells are subsequently simultaneously programmed to a different, second resistive state by applying a second voltage to the first control line that is less than the fixed reference voltage, so that at the conclusion of the respective programming steps a first portion of the memory cells along said column are at the first resistive state and a second portion of the memory cells along said column are at the second resistive state.
摘要翻译：根据各种实施例，一列非易失性存储单元连接在相对的第一和第二控制线之间。将固定的参考电压施加到第二控制线。通过向第一控制线施加大于固定参考电压的第一电压，将存储单元同时编程为第一电阻状态。随后通过向小于固定参考电压的第一控制线施加第二电压而将小于所有存储单元的数据同时编程为不同的第二电阻状态，使得在相应编程步骤结束时，第一部分沿着所述列的存储器单元处于第一电阻状态，并且沿着所述列的存储单元的第二部分处于第二电阻状态。

46. 发明申请

US20110002157A1 RESISTANCE CHANGE TYPE MEMORY 审中-公开
标题翻译：电阻变化型存储器
公开(公告)号：US20110002157A1
公开(公告)日：2011-01-06
申请号：US12881919
申请日：2010-09-14
申请人： Naoharu SHIMOMURA , Yoshiaki Asao
发明人： Naoharu SHIMOMURA , Yoshiaki Asao
IPC分类号： G11C11/21 , G11C11/02
CPC分类号： G11C13/0069 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0028 , G11C13/003 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/72 , G11C2213/74
摘要： A resistance change type memory includes first, second and third drive lines, a resistance change element having one end connected to the third drive line, a first diode having an anode connected to the first drive line and a cathode connected to other end of the first resistance change element, a second diode having an anode connected to other end of the first resistance change element and a cathode connected to the second drive line, and a driver/sinker which supplies a write current to the resistance change element. A write control circuit is arranged such that when first data is written, the write current is caused to flow in a direction from the first drive line to the third drive line, and when second data is written, the write current is caused to flow in a direction from the third drive line to the second drive line.
摘要翻译：电阻变化型存储器包括第一，第二和第三驱动线，电阻改变元件，其一端连接到第三驱动线，第一二极管，具有连接到第一驱动线的阳极和连接到第一驱动线的另一端的阴极电阻变化元件，具有连接到第一电阻变化元件的另一端的阳极和连接到第二驱动线的阴极的第二二极管，以及向电阻变化元件提供写入电流的驱动器/沉降片。写控制电路被布置成使得当第一数据被写入时，使写入电流在从第一驱动线到第三驱动线的方向上流动，并且当写入第二数据时，使写入电流流入从第三驱动线到第二驱动线的方向。

47. 发明授权

US07834410B2 Spin torque transfer magnetic tunnel junction structure 有权
标题翻译：自旋扭矩传递磁隧道结结构
公开(公告)号：US07834410B2
公开(公告)日：2010-11-16
申请号：US12422579
申请日：2009-04-13
申请人： Yu-Jen Wang , Ya-Chen Kao , Chun-Jung Lin
发明人： Yu-Jen Wang , Ya-Chen Kao , Chun-Jung Lin
IPC分类号： H01L29/82 , G11C11/02
CPC分类号： H01L43/08 , G11C11/161 , H01L27/228 , H01L43/12
摘要： The present disclosure provides a semiconductor memory device. The device includes a bottom electrode over a semiconductor substrate; an anti-ferromagnetic layer disposed over the bottom electrode; a pinned layer disposed over the anti-ferromagnetic layer; a barrier layer disposed over the pinned layer; a first ferromagnetic layer disposed over the barrier layer; a buffer layer disposed over the first ferromagnetic layer, the buffer layer including tantalum; a second ferromagnetic layer disposed over the buffer layer; and a top electrode disposed over the second ferromagnetic layer.
摘要翻译：本公开提供一种半导体存储器件。该器件包括在半导体衬底上的底部电极; 设置在底部电极上的反铁磁层; 设置在反铁磁层上的钉扎层; 设置在被钉扎层上的阻挡层; 设置在阻挡层上的第一铁磁层; 设置在所述第一铁磁层上的缓冲层，所述缓冲层包括钽; 设置在所述缓冲层上的第二铁磁层; 以及设置在第二铁磁层上的顶电极。

48. 发明授权

US07755929B2 Spin-injection device and magnetic device using spin-injection device 失效
标题翻译：旋转注射装置和使用自旋注射装置的磁性装置
公开(公告)号：US07755929B2
公开(公告)日：2010-07-13
申请号：US10536437
申请日：2003-11-20
申请人： Kouichiro Inomata , Sadamichi Maekawa , Saburo Takahashi
发明人： Kouichiro Inomata , Sadamichi Maekawa , Saburo Takahashi
IPC分类号： G11C11/02 , G11B5/39 , G11B5/127
CPC分类号： H01L29/66984 , B82Y10/00 , B82Y25/00 , G01R33/06 , G11B5/39 , G11B5/3903 , G11B5/3909 , H01L39/228 , H01L43/08 , Y10T428/1121 , Y10T428/1143 , Y10T428/1193
摘要： First and second tunnel junctions having a common electrode composed of a nonmagnetic conductor and each of which has a counterelectrode composed of a ferromagnet are spaced apart from each other by a distance that is shorter than a spin diffusion length of the nonmagnetic conductor. The first tunnel junction injects spin from the ferromagnet into the nonmagnetic conductor and the second tunnel junction detects, between the ferromagnetic metal and the nonmagnetic conductor, a voltage that accompanies spin injection of the first tunnel junction. The nonmagnetic conductor may be a semiconductor or semimetal that is lower in carrier density than a metal. The common electrode alternatively may be composed of a superconductor. A spin injection device thus provided can exhibit a large signal voltage with a low current and under low magnetic field and can be miniaturized in device size.
摘要翻译：具有由非磁性导体构成的共用电极和具有由铁磁体构成的对电极的公共电极的第一和第二隧道结彼此隔开比非磁性导体的自旋扩散长度短的距离。第一隧道结将铁磁体的旋转注入到非磁性导体中，第二隧道结在铁磁金属和非磁性导体之间检测伴随着第一隧道结的自旋注入的电压。非磁性导体可以是载体密度低于金属的半导体或半金属。公共电极可以由超导体组成。如此提供的自旋注入装置可以以低电流和低磁场显示大信号电压，并且可以在装置尺寸上小型化。

49. 发明授权

US07746687B2 Thermally assisted multi-bit MRAM 有权
标题翻译：热辅助多位MRAM
公开(公告)号：US07746687B2
公开(公告)日：2010-06-29
申请号：US12242254
申请日：2008-09-30
申请人： Yuankai Zheng , Dimitar V. Dimitrov , Haiwen Xi
发明人： Yuankai Zheng , Dimitar V. Dimitrov , Haiwen Xi
IPC分类号： G11C11/02
CPC分类号： G11C11/15 , G11C11/1675 , G11C11/5607
摘要： Methods of writing to a multi-bit MRAM memory unit are described. The method includes to self-detected writing to a multi-bit (i.e., multilevel) thermally assisted MRAM. The self-detected writing increases a reading margin between data state levels and decreases reading margin variability due to cell resistance variation.
摘要翻译：描述写入多位MRAM存储器单元的方法。该方法包括对多位（即多级）热辅助MRAM进行自检测写入。自检的写入会增加数据状态级之间的读取余量，并降低由于单元格电阻变化而导致的读取边缘变化。

50. 发明申请

US20100067283A1 SENSE AMPLIFIER 有权
标题翻译：感应放大器
公开(公告)号：US20100067283A1
公开(公告)日：2010-03-18
申请号：US12624103
申请日：2009-11-23
申请人： Yoshihiro UEDA , Yoshihisa Iwata , Toshiaki Edahiro , Toshihiro Suzuki
发明人： Yoshihiro UEDA , Yoshihisa Iwata , Toshiaki Edahiro , Toshihiro Suzuki
IPC分类号： G11C7/08 , G11C11/00 , G11C11/02 , G11C11/16
CPC分类号： G11C7/065 , G11C7/062 , G11C7/12 , G11C11/1673 , G11C16/0491 , G11C16/26 , G11C17/126 , G11C2207/002 , G11C2207/063
摘要： A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation.
摘要翻译：根据本发明的示例的读出放大器具有触发器连接的第一，第二，第三和第四FET。第五FET的漏极连接到第一输入节点，并且其源极连接到电源节点。第六FET的漏极连接到第二输入节点，其源极连接到电源节点。通过用第一电流从第一输入节点充电第一输出节点并且通过用第二电流从第二输入节点对第二输出节点充电来启动感测操作。开始感测操作后，第五和第六FET导通。

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