专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US07839702B2 Three-dimensional non-volatile register with an oxygen-ion-based memory element and a vertically-stacked register logic 有权
标题翻译：具有基于氧离子的存储元件和垂直堆叠的寄存器逻辑的三维非易失性寄存器
公开(公告)号：US07839702B2
公开(公告)日：2010-11-23
申请号：US12800289
申请日：2010-05-11
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C5/04 , G11C7/062 , G11C13/004 , G11C13/02 , G11C2013/0054 , G11C2013/009 , G11C2207/063 , G11C2213/13 , G11C2213/71
摘要： A non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations.
摘要翻译：非易失性寄存器包括存储元件。存储元件包括第一端和第二端。非易失性寄存器包括与存储元件的第一和第二端相连的寄存器逻辑。寄存器逻辑位于存储器元件下方。存储器元件可以是被配置为将数据存储为可以通过在两个端子上施加读取电压而被非破坏性地确定的多个导电率分布的两端存储器元件。通过在两个端子上施加预定幅度和/或极性的写入电压，可以将新数据写入到两端存储元件。两端存储器元件在没有电源的情况下保留存储的数据。可以使用包括与两端存储元件相同或基本相同的结构的参考元件来产生用于在读取操作期间进行比较的参考信号。

52. 发明申请

US20100293355A1 Fast data access through page manipulation 有权
公开(公告)号：US20100293355A1
公开(公告)日：2010-11-18
申请号：US12804630
申请日：2010-07-26
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F12/00
CPC分类号： G11C5/066 , G11C7/1051 , G11C7/1075 , G11C7/1078 , G11C7/22 , G11C2207/107 , G11C2216/30
摘要： A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data and to generate aligned data, and a page buffer module configured to store the aligned data and, when the page buffer module is full with aligned data, transferring the aligned data to the memory. The method includes receiving data at an interface, aligning the data to generate aligned data, storing aligned data in a page buffer module configured to store aligned data for a write access and retrieved data from a read access, writing aligned data to a memory, and transferring retrieved data to the interface. Data can be transferred by the interface at a first rate and aligned data can be written to or retrieved from the memory at substantially the first rate.

53. 发明申请

US20100195362A1 Non-volatile dual port third dimensional memory 有权
标题翻译：非易失性双端口三维存储器
公开(公告)号：US20100195362A1
公开(公告)日：2010-08-05
申请号：US12592319
申请日：2009-11-23
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C5/02 , G11C11/00 , G11C7/00
CPC分类号： G11C7/1075 , G11C8/14 , G11C8/16
摘要： Non-volatile dual port memory with third dimension memory is described, including a non-volatile third dimensional memory array comprising a memory element, the memory element is configured to change from a first resistive state to a second resistive state in response to a voltage, a transceiver gate configured to gate the voltage to the memory element, the voltage being configured to change the memory element from the first resistive state to the second resistive state, the transceiver gate is configured to receive another voltage from a bit line and a bit bar line, the bit line and the bit bar line being coupled to the memory element and configured to provide the another voltage, and a plurality of word lines coupled to the memory element, the plurality of word lines are configured to provide substantially simultaneous access to the non-volatile third dimensional memory array using two or more ports.
摘要翻译：描述了具有第三维存储器的非易失性双端口存储器，包括包括存储器元件的非易失性第三维存储器阵列，该存储器元件被配置为响应于电压从第一电阻状态改变到第二电阻状态，收发器门被配置为将电压栅极存储到存储器元件，该电压被配置为将存储元件从第一电阻状态改变到第二电阻状态，收发器门被配置为从位线和位条接收另一电压线，位线和位线连接到存储器元件并且被配置为提供另一电压，以及耦合到存储器元件的多个字线，多个字线被配置为提供基本上同时的访问使用两个或多个端口的非易失性第三维存储器阵列。

54. 发明申请

US20100162065A1 Protecting integrity of data in multi-layered memory with data redundancy 审中-公开
标题翻译：通过数据冗余保护多层内存中数据的完整性
公开(公告)号：US20100162065A1
公开(公告)日：2010-06-24
申请号：US12586416
申请日：2009-09-21
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F11/20 , G06F11/00
CPC分类号： H03M7/30 , G11C5/02
摘要： Systems, integrated circuits, and methods for protecting data stored in third dimensional vertically stacked memory technology are disclosed. An integrated circuit is configured to perform duplication of data disposed in multi-layered memory that can comprise two-terminal cross-point memory arrays fabricated BEOL on top of a FEOL logic layer that includes active circuitry for performing data operations (e.g., read, write, program, and erase) on the multi-layered memory. For example, the integrated circuit can include a first subset of BEOL memory layers configured to store data, a second subset of the BEOL memory layers configured to store a copy of the data from the first subset of memory layers, a FEOL redundancy circuit coupled to the first subset of the memory layers and the second subset of the memory layers, the redundancy circuit being configured to provide both a portion of the data and a copy of the portion of the data.
摘要翻译：公开了用于保护存储在第三维垂直堆叠存储器技术中的数据的系统，集成电路和方法。集成电路被配置为执行设置在多层存储器中的数据的复制，其可以包括在包括用于执行数据操作的有源电路（例如，读取，写入）的FEOL逻辑层之上制造的BEOL的两端交叉点存储器阵列，程序和擦除）在多层内存上。例如，集成电路可以包括被配置为存储数据的BEOL存储器层的第一子集，BEOL存储器层的第二子集被配置为存储来自存储器层的第一子集的数据的副本，耦合到存储器层的第一子集和存储器层的第二子集，冗余电路被配置为提供数据的一部分和数据的该部分的副本。

55. 发明申请

US20100157670A1 High voltage switching circuitry for a cross-point array 有权
标题翻译：用于交叉点阵列的高压开关电路
公开(公告)号：US20100157670A1
公开(公告)日：2010-06-24
申请号：US12653899
申请日：2009-12-18
申请人： Christophe Chevallier , Chang Hua Siau
发明人： Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C16/06 , G11C7/00 , G11C16/04
CPC分类号： G11C13/0023 , G11C8/08 , G11C8/10 , G11C13/0007 , G11C13/0028 , G11C2213/31 , G11C2213/71 , G11C2213/77 , H03K3/356104 , H03K19/018521
摘要： Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example.
摘要翻译：公开了用于产生用于对非易失性可重写存储器阵列执行数据操作的电压电平的电路。在一些实施例中，集成电路包括衬底和形成在衬底上的基底层，以包括被配置为在第一电压范围内操作的有源器件。此外，集成电路可以包括形成在基极层上方的交叉点存储器阵列，并且包括可重写的两端存储器单元，其被配置为例如在大于第一电压范围的第二电压范围内操作。交叉点存储器阵列中的导电阵列线与基极层中的有源器件电耦合。集成电路还可以包括X线解码器和Y线解码器，其中包括在第一电压范围内工作的器件。有源器件可以包括其他有源电路，例如用于从存储器单元读取数据的感测放大器。

56. 发明申请

US20100157644A1 Configurable memory interface to provide serial and parallel access to memories 审中-公开
标题翻译：可配置的存储器接口提供串行和并行访问存储器
公开(公告)号：US20100157644A1
公开(公告)日：2010-06-24
申请号：US12587841
申请日：2009-10-13
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C5/02 , G11C7/00 , G11C5/06
CPC分类号： G11C7/1045 , G11C5/00 , G11C7/10 , G11C8/10
摘要： The invention relates to an interface for providing multiple modes of accessing data, including serial and parallel modes. Controllable non-volatile memory interfaces are described, including a serial module configured to provide a serial connection between a non-volatile memory array and another non-volatile memory array. The serial module can provide access to the non-volatile memory array. A mode module can be configured to determine which type of interface operation (i.e., serial mode or parallel mode) will be used for the non-volatile memory array and the another non-volatile memory array. In some cases, a controller can be configured to select the serial module independent of the mode module. Circuitry for performing data operations on the non-volatile memories can be fabricated FEOL on a substrate and the non-volatile memories can be fabricated BEOL directly on top of the substrate in one or more layers of memory.
摘要翻译：本发明涉及一种用于提供多种访问数据模式的接口，包括串行和并行模式。描述了可控非易失性存储器接口，包括被配置为提供非易失性存储器阵列与另一非易失性存储器阵列之间的串行连接的串行模块。串行模块可以提供对非易失性存储器阵列的访问。可以将模式模块配置为确定将用于非易失性存储器阵列和另一非易失性存储器阵列的哪种类型的接口操作（即串行模式或并行模式）。在某些情况下，控制器可以配置为独立于模式模块选择串行模块。用于对非易失性存储器执行数据操作的电路可以在衬底上制造为FEOL，并且非易失性存储器可以在一个或多个存储器层中直接在衬底的顶部上制造BEOL。

57. 发明授权

US07652501B2 Programmable logic device structure using third dimensional memory 有权
标题翻译：使用第三维存储器的可编程逻辑器件结构
公开(公告)号：US07652501B2
公开(公告)日：2010-01-26
申请号：US12008077
申请日：2008-01-07
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F7/38
CPC分类号： H03K19/1776 , H03K19/17748 , H03K19/1778 , H03K19/17796
摘要： A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate.
摘要翻译：公开了一种使用第三维存储器的可编程逻辑器件（PLD）结构。 PLD结构包括被配置为将信号的极性（例如，施加到输入的输入信号）耦合到路由线路的开关和被配置为控制开关的非易失性寄存器。非易失性寄存器可以包括诸如第三维存储元件的非易失性存储元件。非易失性存储器元件可以是在没有电力的情况下保存存储的数据并将数据存储为可以通过在两个端子上施加读取电压而被非破坏性地感测的多个电导率分布的两端存储元件。可以通过在两个端子上施加写入电压将新数据写入到两端存储元件。逻辑和其它有源电路可以被定位在衬底中，并且非易失性存储元件可以被定位在衬底的顶部上。

58. 发明申请

US20090303772A1 Two-Terminal Reversibly Switchable Memory Device 审中-公开
标题翻译：双端可逆切换存储器
公开(公告)号：US20090303772A1
公开(公告)日：2009-12-10
申请号：US12456627
申请日：2009-06-18
申请人： Darrell Rinerson , Christophe Chevallier , Wayne Kinney , Roy Lambertson , John E. Sanchez, JR. , Lawrence Schloss , Philip Swab , Edmond Ward
发明人： Darrell Rinerson , Christophe Chevallier , Wayne Kinney , Roy Lambertson , John E. Sanchez, JR. , Lawrence Schloss , Philip Swab , Edmond Ward
IPC分类号： G11C11/00 , H01L45/00 , G11C7/00
CPC分类号： H01L45/08 , G06F17/5045 , G11C11/5685 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/005 , G11C2013/009 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/54 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1625
摘要： A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
摘要翻译：公开了使用混合价态导电氧化物的记忆体。存储器包括在其缺氧状态下导电性较差的混合价态导电氧化物和作为电解质的氧的混合电子离子导体并且促进有效引起氧离子运动的电场。

59. 发明授权

US07593284B2 Memory emulation using resistivity-sensitive memory 有权
公开(公告)号：US07593284B2
公开(公告)日：2009-09-22
申请号：US11975275
申请日：2007-10-17
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C8/00
CPC分类号： G06F13/4239 , G06F13/1694 , G11C7/10 , G11C7/22 , Y02D10/14 , Y02D10/151
摘要： Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another.

60. 发明申请

US20090225582A1 Data retention structure for non-volatile memory 失效
标题翻译：非易失性存储器的数据保留结构
公开(公告)号：US20090225582A1
公开(公告)日：2009-09-10
申请号：US12075017
申请日：2008-03-07
申请人： Lawrence Schloss
发明人： Lawrence Schloss
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C2213/71 , G11C2213/77 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： A data retention structure in a memory element that stores data as a plurality of conductivity profiles is disclosed. The memory element can be used in a variety of electrical systems and includes a conductive oxide layer, an ion impeding layer, and an electrolytic tunnel barrier layer. A write voltage applied across the memory element causes a portion of the mobile ions to move from the conductive oxide layer, through the ion impeding layer, and into the electrolytic tunnel barrier layer thereby changing a conductivity of the memory element, or the write voltage causes a quantity of the mobile ions to move from the electrolytic tunnel barrier layer, through the ion impeding layer, and back into the conductive oxide layer. The ion impeding layer is operative to substantially stop mobile ion movement when a voltage that is less than the write voltage is applied across the memory element.
摘要翻译：公开了存储数据作为多个导电率分布的存储元件中的数据保持结构。存储元件可用于各种电气系统中，并且包括导电氧化物层，离子阻挡层和电解隧道势垒层。施加在存储元件两端的写入电压使得一部分移动离子从导电氧化物层移动通过离子阻挡层，并进入电解隧道阻挡层，从而改变存储元件的导电性，或者写入电压导致一定量的移动离子从电解隧道阻挡层移动通过离子阻挡层，并返回到导电氧化物层中。当超过写入电压的电压跨越存储元件施加时，离子阻挡层可操作以基本上停止移动离子的移动。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式