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51. 发明授权

US08072814B2 NAND with back biased operation 有权
标题翻译： NAND具有反向偏置运算
公开(公告)号：US08072814B2
公开(公告)日：2011-12-06
申请号：US12771211
申请日：2010-04-30
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/10
摘要： Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of the circuitry are biased at zero volts.
摘要翻译：公开了编程，读取和擦除存储器单元的方法。在至少一个实施例中，存储器中的程序，感测和擦除操作是通过反向偏置操作进行的，例如改进串驱动器和位线驱动器中的高电压器件隔离和截止，并且电路的任何节点都不偏零伏。

52. 发明申请

US20110280085A1 MEMORY DEVICE HAVING IMPROVED PROGRAMMING OPERATION 有权
标题翻译：具有改进的编程操作的存储器件
公开(公告)号：US20110280085A1
公开(公告)日：2011-11-17
申请号：US13193192
申请日：2011-07-28
申请人： Prashant S. Damle , Krishna Parat , Alessandro Torsi , Carlo Musilli , Kalpana Vakati , Akira Goda
发明人： Prashant S. Damle , Krishna Parat , Alessandro Torsi , Carlo Musilli , Kalpana Vakati , Akira Goda
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/3404 , G11C16/0483 , G11C16/10 , G11C16/32
摘要： Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.
摘要翻译：一些实施例包括具有模块和存储器单元的方法和装置。该模块被配置为在编程操作期间减少存储器单元的源极和漏极中的电子量。

53. 发明申请

US20110149654A1 NAND Programming Technique 有权
标题翻译： NAND编程技术
公开(公告)号：US20110149654A1
公开(公告)日：2011-06-23
申请号：US12644408
申请日：2009-12-22
申请人： Akira Goda , Andrew Bickler , Haitao Liu , Tomoharu Tanaka
发明人： Akira Goda , Andrew Bickler , Haitao Liu , Tomoharu Tanaka
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3418 , G11C16/0408 , G11C16/06
摘要： A NAND memory array is programmed applying a programming voltage Vpgm as a double pulse programming pulse if a data pattern associated with memory cells that are to be programmed form a two-sided column-stripe (CS2) data pattern. The CS2 data pattern comprises a memory cell that is not to be programmed directly between two memory cells that are to be programmed, such that a channel associated with the memory cell that is not to be programmed has an applied boost voltage, and the channels associated with the two memory cells that are to be programmed have an applied programming voltage. The first memory cell of the two memory cells is programmed by the first programming voltage pulse and the second memory cell is programmed by the second programming voltage pulse. A programming voltage Vpgm is applied as a single pulse if a CS2 data pattern is not formed.
摘要翻译：如果与要编程的存储器单元相关联的数据模式形成双面列条带（CS2）数据模式，则NAND存储器阵列被编程为将编程电压Vpgm应用为双脉冲编程脉冲。 CS2数据模式包括不被直接编程在待编程的两个存储器单元之间的存储器单元，使得与不被编程的存储器单元相关联的通道具有施加的升压电压，并且所述通道相关联要编程的两个存储单元具有应用的编程电压。两个存储单元的第一存储单元由第一编程电压脉冲编程，第二存储单元由第二编程电压脉冲编程。如果没有形成CS2数据模式，则将编程电压Vpgm作为单个脉冲施加。

54. 发明授权

US07923364B2 Tunnel dielectric comprising nitrogen for use with a semiconductor device and a process for forming the device 有权
标题翻译：包含用于半导体器件的氮的隧道电介质和用于形成该器件的工艺
公开(公告)号：US07923364B2
公开(公告)日：2011-04-12
申请号：US12644250
申请日：2009-12-22
申请人： Akira Goda
发明人： Akira Goda
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/82385 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS transistor comprising gate oxide and having a wide active area and/or a long channel, and the second transistor type may comprise a NAND comprising tunnel oxide and having a narrow active area and/or short gate length. The transistors are exposed to a nitridation ambient. Various process embodiments and completed structures are disclosed.
摘要翻译：在半导体器件制造期间使用的方法包括形成至少两种类型的晶体管。第一晶体管类型可以包括包含栅极氧化物并具有宽有源面积和/或长沟道的CMOS晶体管，并且第二晶体管类型可以包括具有隧道氧化物的NAND并且具有窄的有源面积和/或短栅极长度。晶体管暴露于氮化环境。公开了各种处理实施例和完成的结构。

55. 发明申请

US20100220528A1 NAND WITH BACK BIASED OPERATION 有权
标题翻译： NAND带反向偏移操作
公开(公告)号：US20100220528A1
公开(公告)日：2010-09-02
申请号：US12771211
申请日：2010-04-30
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/10
摘要： Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of the circuitry are biased at zero volts
摘要翻译：公开了编程，读取和擦除存储器单元的方法。在至少一个实施例中，存储器中的程序，感测和擦除操作是通过反向偏置操作进行的，例如改进串驱动器和位线驱动器中的高电压器件隔离和截止，并且电路的任何节点都不偏零伏

56. 发明申请

US20100099235A1 Tunnel Dielectric Comprising Nitrogen For Use With A Semiconductor Device And A Process For Forming The Device 有权
标题翻译：包含用于半导体器件的氮的隧道介质和用于形成该器件的工艺
公开(公告)号：US20100099235A1
公开(公告)日：2010-04-22
申请号：US12644250
申请日：2009-12-22
申请人： Akira Goda
发明人： Akira Goda
IPC分类号： H01L21/762 , H01L21/28
CPC分类号： H01L21/76229 , H01L21/82385 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS transistor comprising gate oxide and having a wide active area and/or a long channel, and the second transistor type may comprise a NAND comprising tunnel oxide and having a narrow active area and/or short gate length. The transistors are exposed to a nitridation ambient. Various process embodiments and completed structures are disclosed.
摘要翻译：在半导体器件制造期间使用的方法包括形成至少两种类型的晶体管。第一晶体管类型可以包括包含栅极氧化物并具有宽有源面积和/或长沟道的CMOS晶体管，并且第二晶体管类型可以包括具有隧道氧化物的NAND并且具有窄的有源面积和/或短栅极长度。晶体管暴露于氮化环境。公开了各种处理实施例和完成的结构。

57. 发明申请

US20090296471A1 MEMORY CELL OPERATION 有权
标题翻译：记忆体操作
公开(公告)号：US20090296471A1
公开(公告)日：2009-12-03
申请号：US12127415
申请日：2008-05-27
申请人： Akira Goda , Andrei Mihnea
发明人： Akira Goda , Andrei Mihnea
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/06 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/10 , G11C2211/5621 , G11C2211/5634
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.
摘要翻译：本公开的实施例提供用于操作存储器单元的方法，设备，模块和系统。一种方法包括：对所选择的一组存储器单元执行擦除操作，所选择的组包括多个参考单元和多个数据单元; 对作为擦除操作的一部分的参考单元的数量进行编程监视操作; 以及至少部分地基于对参考单元的数量执行的编程监视操作来确定与操作所述数据单元的数量相关联的特定操作参数的数量。

58. 发明申请

US20090267136A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20090267136A1
公开(公告)日：2009-10-29
申请号：US12498149
申请日：2009-07-06
申请人： Akira Goda , Mitsuhiro Noguchi
发明人： Akira Goda , Mitsuhiro Noguchi
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11568 , H01L27/11573
摘要： A semiconductor memory device having a memory cell region and a peripheral circuit region, and a method of manufacturing such a semiconductor memory device, are proposed, in which trench grooves are formed to be shallow in the memory cell region in order to improve the yield, and trench grooves are formed to be deep in the high voltage transistor region of the peripheral circuit region, in particular in a high voltage transistor region thereof, in order to improve the element isolation withstand voltage. A plurality of memory cell transistors having an ONO layer 15 serving as a charge accumulating insulating layer are provided in the memory cell region, where element isolation grooves 6 for these memory cell transistors are narrow and shallow. Two types of transistors, one for high voltage and the other for low voltage, having gate insulating layers 16 or 17, which are different from the ONO layer 15 in the memory cell region, are provided in the peripheral circuit region, where at least element isolation grooves 23 for high voltage transistors are wide and deep. In this way, it is possible to improve the degree of integration and yield in the memory cell region, and secure withstand voltage in the peripheral circuit region.
摘要翻译：提出了具有存储单元区域和外围电路区域的半导体存储器件以及制造这种半导体存储器件的方法，其中沟槽形成在存储单元区域中较浅以提高产量，并且在周边电路区域的高电压晶体管区域，特别是在其高压晶体管区域中形成深沟槽，以便提高元件隔离耐受电压。在存储单元区域中设置有多个具有作为电荷累积绝缘层的ONO层15的存储单元晶体管，其中用于这些存储单元晶体管的元件隔离槽6窄而浅。在外围电路区域中设置两个类型的晶体管，一个用于高电压，另一个用于低电压，具有与存储单元区域中的ONO层15不同的栅极绝缘层16或17，其中至少元件用于高压晶体管的隔离槽23宽而深。以这种方式，可以提高存储单元区域的集成度和产量，并且确保外围电路区域中的耐受电压。

59. 发明申请

US20080273385A1 NAND step up voltage switching method 有权
标题翻译： NAND升压电压切换方式
公开(公告)号：US20080273385A1
公开(公告)日：2008-11-06
申请号：US11800002
申请日：2007-05-03
申请人： Akira Goda , Taehoon Kim , Doyle Rivers , Roger Porter
发明人： Akira Goda , Taehoon Kim , Doyle Rivers , Roger Porter
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C5/145 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621
摘要： Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.
摘要翻译：具有用于根据正在编程的多电平单元的电平改变Vstep增量的切换点的方法和存储器包括在窄阈值电压情况下以较小的Vstep增量进行编程，并且在需要更快编程的较大Vstep增量下进行编程。

60. 发明申请

US20080122098A1 Nonvolatile semiconductor memory and method for fabricating the same 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20080122098A1
公开(公告)日：2008-05-29
申请号：US12000396
申请日：2007-12-12
申请人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
发明人： Minori Kajimoto , Mitsuhiro Noguchi , Akira Goda
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L27/11568 , H01L21/76838 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.
摘要翻译：非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

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