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51. 发明授权

US07751221B2 Media player with non-volatile memory 有权
公开(公告)号：US07751221B2
公开(公告)日：2010-07-06
申请号：US12004737
申请日：2007-12-21
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C5/02
CPC分类号： G11C5/04 , G11C5/02
摘要： A media player is provided that includes a processor configured to execute a media player program, a non-volatile memory electrically coupled with the processor, the non-volatile memory being vertically configured, an input/output module electrically coupled with the processor and the non-volatile memory and configured to communicate with an input/output device, and an analog/digital module electrically coupled with the processor and the non-volatile memory, the analog/digital module configured to output a media signal. The input/output module may be in electrical communication with the input/output device (e.g., electrically coupled) and/or signal communication with the input/output device (e.g., wireless and/or optical communication).

52. 发明申请

US20100157659A1 Digital potentiometer using third dimensional memory 失效
标题翻译：数字电位器采用三维存储器
公开(公告)号：US20100157659A1
公开(公告)日：2010-06-24
申请号：US12653897
申请日：2009-12-18
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： H03G1/0088 , H03G3/001 , H03H11/24
摘要： A digital potentiometer using third dimensional memory includes a switch configured to electrically couple one or more resistive elements with a first pin and a second pin, and a non-volatile register configured to control the switch. In one example, the non-volatile register can include a BEOL non-volatile memory element, such as a third dimensional memory element. The non-volatile register can include a FEOL active circuitry portion that is electrically coupled with the BEOL non-volatile memory element to implement the non-volatile register. The resistive elements can be BEOL resistive elements that can be fabricated on the same plane or a different plane than the BEOL non-volatile memory elements. The BEOL non-volatile memory elements and the BEOL resistive elements can retain stored data in the absence of power and the stored data can be non-destructively determined by application of a read voltage.
摘要翻译：使用第三维存储器的数字电位器包括被配置为将一个或多个电阻元件与第一引脚和第二引脚电耦合的开关以及被配置为控制开关的非易失性寄存器。在一个示例中，非易失性寄存器可以包括诸如第三维存储器元件的BEOL非易失性存储器元件。非易失性寄存器可以包括与BEOL非易失性存储器元件电耦合以实现非易失性寄存器的FEOL有源电路部分。电阻元件可以是可以制造在与BEOL非易失性存储器元件相同的平面或不同平面上的BEOL电阻元件。 BEOL非易失性存储器元件和BEOL电阻元件可以在没有电力的情况下保留存储的数据，并且存储的数据可以通过应用读取电压而非破坏性地确定。

53. 发明申请

US20100134144A1 Field programmable gate arrays using resistivity sensitive memories 有权
公开(公告)号：US20100134144A1
公开(公告)日：2010-06-03
申请号：US12657678
申请日：2010-01-25
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , H03K19/1776 , H03K19/17772 , H03K19/1778
摘要： Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane.

54. 发明授权

US07719876B2 Preservation circuit and methods to maintain values representing data in one or more layers of memory 有权
标题翻译：保存电路和保持在一层或多层存储器中表示数据的值的方法
公开(公告)号：US07719876B2
公开(公告)日：2010-05-18
申请号：US12221136
申请日：2008-07-31
申请人： Christophe J. Chevallier , Robert Norman
发明人： Christophe J. Chevallier , Robert Norman
IPC分类号： G11C7/00
CPC分类号： G11C13/0035 , G11C5/005 , G11C5/02 , G11C11/16 , G11C13/0002 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/71 , G11C2213/77
摘要： Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.
摘要翻译：公开了用于恢复存储器中的数据的电路和方法。存储器可以包括非易失性两端交叉点阵列的至少一层，其包括将数据存储为多个电导率分布并且在没有电力的情况下保存存储的数据的多个两端存储器元件。在一段时间内，指示存储的数据的逻辑值可能漂移，使得如果逻辑值不被恢复，则所存储的数据可能被破坏。每个存储器的至少一部分可以具有与存储器电耦合的电路重写或恢复的数据。可以使用其他电路来确定用于对存储器执行恢复操作的调度，并且恢复操作可以由内部或外部信号或事件来触发。电路可以定位在逻辑层中，并且存储器可以在逻辑层上制造。

55. 发明授权

US07715250B2 Circuitry and method for indicating a memory 失效
公开(公告)号：US07715250B2
公开(公告)日：2010-05-11
申请号：US11893647
申请日：2007-08-16
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C7/00
CPC分类号： G06F12/06 , G06F13/1694 , G11C11/005 , Y02D10/13 , Y02D10/14
摘要： Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of vertically stacked memory planes. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power.

56. 发明授权

US07652502B2 Field programmable gate arrays using resistivity sensitive memories 有权
标题翻译：使用电阻率敏感存储器的现场可编程门阵列
公开(公告)号：US07652502B2
公开(公告)日：2010-01-26
申请号：US12006006
申请日：2007-12-29
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , H03K19/1776 , H03K19/17772 , H03K19/1778
摘要： Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane.
摘要翻译：描述了使用电阻率敏感存储器的现场可编程门阵列，包括包括可配置逻辑的可编程单元，连接到可配置逻辑以提供可配置逻辑的功能的存储器，存储器包括非易失性可重写存储元件，敏感存储器元件，连接到可配置逻辑的输入/输出逻辑和与其他单元通信的存储器。存储器元件可以是在没有电力的情况下存储数据的两端电阻率敏感存储器元件。两端存储器元件可以将数据存储为可以通过在存储器元件的端子上施加读取电压而被非破坏性地读取的多个导电率分布，并且可以通过施加写入电压将数据写入到两端存储器元件跨越终端。存储器可以垂直配置在一个或多个垂直堆叠在一起的并且位于逻辑平面之上的存储器平面中。

57. 发明申请

US20090196087A1 Non-volatile register 有权
标题翻译：非易失性寄存器
公开(公告)号：US20090196087A1
公开(公告)日：2009-08-06
申请号：US12012641
申请日：2008-02-05
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C11/21 , G11C7/00
CPC分类号： G11C13/0069 , G11C5/04 , G11C7/062 , G11C13/004 , G11C13/02 , G11C2013/0054 , G11C2013/009 , G11C2207/063 , G11C2213/13 , G11C2213/71
摘要： A non-volatile register is disclosed. The non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations.
摘要翻译：公开了一种非易失性寄存器。非易失性寄存器包括存储元件。存储元件包括第一端和第二端。非易失性寄存器包括与存储元件的第一和第二端相连的寄存器逻辑。寄存器逻辑位于存储器元件下方。存储器元件可以是被配置为将数据存储为可以通过在两个端子上施加读取电压而被非破坏性地确定的多个导电率分布的两端存储器元件。通过在两个端子上施加预定幅度和/或极性的写入电压，可以将新数据写入到两端存储元件。两端存储器元件在没有电源的情况下保留存储的数据。可以使用包括与两端存储元件相同或基本相同的结构的参考元件来产生用于在读取操作期间进行比较的参考信号。

58. 发明申请

US20090175084A1 Buffering systems for accessing multiple layers of memory in integrated circuits 有权
标题翻译：用于在集成电路中访问多层存储器的缓冲系统
公开(公告)号：US20090175084A1
公开(公告)日：2009-07-09
申请号：US12006970
申请日：2008-01-08
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C7/1006 , G06F13/1668 , G11C5/025 , G11C7/1012 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C2207/2218
摘要： Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.
摘要翻译：本发明的实施例一般涉及数据存储和计算机存储器，更具体地，涉及用于访问实现例如第三维存储器技术的多层存储器中的存储器的系统，集成电路和方法。在具体实施例中，集成电路被配置为实现写入缓冲器以访问多层存储器。例如，集成电路可以包括设置在多层存储器中的存储单元。在一个实施例中，存储器单元可以是第三维存储器单元。集成电路还可以包括可以与写入缓冲器不同的读取缓冲器。在至少一个实施例中，写入缓冲器的大小可以作为写周期的函数。每层存储器可以包括多个两端存储元件，其在不存在功率的情况下保存存储的数据，并将数据存储为多个导电率分布。

59. 发明申请

US20090172350A1 Non-volatile processor register 审中-公开
标题翻译：非易失性处理器寄存器
公开(公告)号：US20090172350A1
公开(公告)日：2009-07-02
申请号：US12005685
申请日：2007-12-28
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G06F9/00
CPC分类号： G06F9/30141 , G06F1/30 , G06F9/30101 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/3851 , G06F9/3863 , G11C14/00
摘要： A processor using a vertically configured non-volatile memory array that can retain values through a power failure is disclosed. The processor may include a register block configured to store and retrieve one or more values, the register block being a vertically configured non-volatile memory array, an arithmetic block configured to perform an arithmetic operation on the one or more values, and a control block configured to control the register block, the arithmetic block, and a memory block. The vertically configured non-volatile memory array may include a plurality of two-terminal memory elements. The two-terminal memory elements may be resistivity-sensitive and store data in the absence of power. The two-terminal memory elements store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written by applying a write voltage across the terminals.
摘要翻译：公开了一种使用可以通过电源故障保持值的垂直配置的非易失性存储器阵列的处理器。处理器可以包括被配置为存储和检索一个或多个值的寄存器块，寄存器块是垂直配置的非易失性存储器阵列，被配置为对一个或多个值执行算术运算的算术块，以及控制块配置为控制寄存器块，算术块和存储块。垂直配置的非易失性存储器阵列可以包括多个两端存储器元件。两端存储元件可以是电阻率敏感的并且在没有电力的情况下存储数据。两端存储器元件将数据存储为可以通过在存储元件的端子上施加读取电压而被非破坏性地读取的多个导电率分布，并且可以通过在端子上施加写入电压来写入数据。

60. 发明申请

US20090167353A1 State machines using resistivity-sensitive memories 失效
标题翻译：使用电阻率敏感记忆的状态机
公开(公告)号：US20090167353A1
公开(公告)日：2009-07-02
申请号：US12006199
申请日：2007-12-30
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H03K19/08
CPC分类号： G05B19/045 , G05B2219/23289 , G11C13/00
摘要： State machines using resistivity-sensitive memory elements are disclosed. The state machine includes a next state logic comprising a non-volatile memory including a resistivity-sensitive memory element and receiving an input, a state storage device connected to the next state logic including a connection to provide a state of the state machine to the next state logic, and an output connect to the state register to output the state of the state machine. The resistivity-sensitive memory elements may be two-terminal resistivity-sensitive memory elements. The two-terminal resistivity-sensitive memory elements may store data as a plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory elements, and new data can be written by applying a write voltage across the terminals. The two-terminal resistivity-sensitive memory elements retain stored data in the absence of power and may be configured into a two-terminal cross-point memory array.
摘要翻译：公开了使用电阻率敏感记忆元件的状态机。状态机包括下一状态逻辑，其包括包括电阻率敏感存储元件和接收输入的非易失性存储器，连接到下一状态逻辑的状态存储设备，该状态存储器包括连接以将状态机的状态提供给下一个状态状态逻辑，输出连接到状态寄存器以输出状态机的状态。电阻率敏感存储元件可以是两端电阻率敏感存储元件。两端电阻率敏感存储器元件可以将数据存储为可以通过在存储器元件的端子上施加读取电压而被非破坏性读取的多个导电率分布，并且可以通过施加写入电压来写入新的数据终端。两端电阻率敏感存储器元件在没有电力的情况下保存存储的数据，并且可以被配置为两端交叉点存储器阵列。

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