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51. 发明授权

US10077188B2 Manufacturing method of MEMS chip 有权
公开(公告)号：US10077188B2
公开(公告)日：2018-09-18
申请号：US15405603
申请日：2017-01-13
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Dan Dai , Xinwei Zhang , Guoping Zhou , Changfeng Xia
IPC分类号： B81C1/00
CPC分类号： B81C1/00825 , B81B7/0029 , B81C1/0038 , B81C2201/0167 , B81C2201/053
摘要： A method of manufacturing a MEMS chip includes: providing a silicon substrate layer, the silicon substrate layer comprising a front surface configured to perform a MEMS process and a rear surface opposite to the front surface; growing a first oxidation layer mainly made of SiO2 on the rear surface of the silicon substrate layer by performing a thermal oxidation process; and depositing a first thin film layer mainly made of silicon nitride on the first oxidation layer by performing a low pressure chemical vapor deposition process.

52. 发明授权

US10019027B2 Direct digital synthesizing method and direct digital synthesizer 有权
公开(公告)号：US10019027B2
公开(公告)日：2018-07-10
申请号：US15325855
申请日：2015-06-30
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Huagang Wu
IPC分类号： G06F1/03 , H03L7/16
CPC分类号： G06F1/0321 , G06F1/022 , H03L7/16
摘要： A direct digital frequency synthesis method comprises the following steps: calculating, by a phase accumulation module, a first phase according to a frequency synthesis word (S101); finding an amplitude value by a preset sinusoidal lookup table according to the first phase (S102); finding a second phase by a preset phase lookup table according to the amplitude value (S103); if the second phase is less than the first phase, adjusting and outputting the amplitude value (S105); or else, outputting the original amplitude value (S106); and performing, by a digital-to-analog converter, a digital-to-analog conversion according to the output amplitude value to obtain a sinusoidal wave (S107); wherein, for a N-bit phase accumulation module and a D-bit digital-to-analog converter, the preset phase lookup table has 2D−1-1 phase boundary value records corresponding to 0˜2D−1-2 amplitudes, each phase boundary value is stored in N-2 bits. A direct digital frequency synthesizer applying the above method is also disclosed.

53. 发明授权

US09960047B2 Test pattern for trench poly over-etched step and formation method thereof 有权
公开(公告)号：US09960047B2
公开(公告)日：2018-05-01
申请号：US14236473
申请日：2012-06-07
申请人： Zheng Bian
发明人： Zheng Bian
IPC分类号： H01L21/66 , H01L21/306
CPC分类号： H01L21/30604 , H01L22/12 , H01L22/30
摘要： A test pattern for testing a trench POLY over-etched step is provided. The test pattern is a trench (14) formed on a substrate (1); the trench (14) comprises a bottom surface and two side surfaces extending from the bottom surface; the trench (14) is formed on the substrate (1) with a preset angle of non-90° formed between the longitudinal direction (L) thereof and the longitudinal direction (X) of a wafer scribing trench. The test pattern can extend the scanning length of a step scanning equipment without changing the width of the trench.

54. 发明授权

US09953970B2 Semiconductor device having ESD protection structure 有权
公开(公告)号：US09953970B2
公开(公告)日：2018-04-24
申请号：US15308574
申请日：2015-05-04
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Guangsheng Zhang , Sen Zhang
IPC分类号： H01L27/02 , H01L23/60 , H01L29/73 , H01L23/535 , H01L29/739
CPC分类号： H01L27/027 , H01L23/535 , H01L23/60 , H01L27/0266 , H01L29/7393 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates to a semiconductor device with an ESD protection structure. The semiconductor device includes a high-voltage power device 101, the ESD protection structure is a NMOS transistor 102, a drain of the NMOS transistor is shared by a source of the power device as a common-drain-source structure 107, substrate leading-out regions of the power device 101 and the NMOS transistor are coupled to the source 106 of the NMOS transistor as a ground leading-out. In the present disclosure, the drain of the NMOS transistor is shared by the source of the power device, so the increased area of the device with the ESD protection structure incorporated is small. In addition, the holding voltage at the source of the high-voltage power device is relatively low, which helps to protect the gate oxide and improve the source reliability.

55. 发明授权

US09905680B2 Lateral insulated-gate bipolar transistor 有权
公开(公告)号：US09905680B2
公开(公告)日：2018-02-27
申请号：US15538450
申请日：2015-09-10
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shukun Qi
IPC分类号： H01L29/739 , H01L29/08
CPC分类号： H01L29/7394 , H01L29/0834 , H01L29/7393
摘要： A lateral insulated gate bipolar transistor comprises a substrate (10); an anode terminal located on the substrate, comprising: an N-type buffer region (51) located on the substrate (10); a P well (53) located in the N-type buffer region; an N-region (55) located in the P well (53); two P+ shallow junctions (57) located on a surface of the P well (53); and an N+ shallow junction (59) located between the two P+ shallow junctions (57); a cathode terminal located on the substrate; a draft region (30) between the anode terminal and cathode terminal; and a gate (62) between the anode terminal and cathode terminal.

56. 发明申请

US20170271505A1 N-TYPE LATERAL DOUBLE-DIFFUSED METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR 审中-公开
公开(公告)号：US20170271505A1
公开(公告)日：2017-09-21
申请号：US15320589
申请日：2015-07-31
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Xiaolong HU , Guangsheng ZHANG , Peng BIAN , Sen ZHANG
IPC分类号： H01L29/78 , H01L29/40 , H01L29/49 , H01L29/10
CPC分类号： H01L29/7816 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/408 , H01L29/42368 , H01L29/4916 , H01L29/735 , H01L29/7831
摘要： An N type lateral double-diffused metal oxide semiconductor field effect transistor (200) includes a substrate (202); a first N well (204) formed on the substrate; a second N well (206), a first P well (208), a third N well (210) and a fourth N well (212); a source lead-out region (214) formed on the first P well (208); a drain lead-out region (216) formed on the fourth N well (212); a first gate lead-out region formed on surfaces of the second N well (206) and the first P well (208); and a second gate lead-out region formed on surfaces of the first P well (208) and the third N well (210). The first gate lead-out region and the second gate lead-out region are respectively led out by means of metal wires, and then are connected to serve as a gate.

57. 发明授权

US09601336B2 Trench field-effect device and method of fabricating same 有权
公开(公告)号：US09601336B2
公开(公告)日：2017-03-21
申请号：US14376021
申请日：2012-07-18
申请人： Hongwei Zhou , Dongyue Gao
发明人： Hongwei Zhou , Dongyue Gao
IPC分类号： H01L21/28 , H01L29/423 , H01L29/66 , H01L29/78
CPC分类号： H01L21/28229 , H01L29/4236 , H01L29/42368 , H01L29/66734 , H01L29/7813 , H01L29/7827
摘要： The present invention provides a method of fabricating a trench field-effect device. The method includes: providing a substrate including an epitaxial layer formed on a semiconductor substrate of the substrate and a trench formed in the epitaxial layer; forming a sacrificial dielectric layer on a bottom and a sidewall of the trench; forming a heavily-doped polysilicon region at the bottom, and removing part of the sacrificial dielectric layer not covered by the heavily-doped polysilicon region to expose an epitaxial layer of the sidewall; and oxidizing the heavily-doped polysilicon region and the epitaxial layer simultaneously and forming a thick oxide layer and a trench sidewall gate dielectric layer synchronously on the bottom and the sidewall, respectively; wherein thickness of the thick oxide layer is greater than that of the trench sidewall gate dielectric layer. The method is simple, and figure of merit of the fabricated trench field-effect device is reduced.

58. 发明授权

US09443926B2 Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor 有权
标题翻译：场阻反向绝缘栅双极晶体管及其制造方法
公开(公告)号：US09443926B2
公开(公告)日：2016-09-13
申请号：US14901606
申请日：2014-06-06
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shuo Zhang , Qiang Rui , Xiaoshe Deng , Genyi Wang
IPC分类号： H01L29/74 , H01L29/06 , H01L29/66 , H01L29/739 , H01L23/528 , H01L23/532 , H01L23/31
CPC分类号： H01L29/0607 , H01L23/3157 , H01L23/3171 , H01L23/528 , H01L23/53219 , H01L23/53247 , H01L29/0619 , H01L29/0834 , H01L29/66325 , H01L29/66333 , H01L29/7393 , H01L29/7395
摘要： A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method thereof. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer (1) departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure (10) is provided with a back-surface metal layer (12). A plurality of polysilicon filling structures (11) which penetrate into the electric field stop layer (1) from the back-surface P-type structure (10) are formed in the active region (100).
摘要翻译：场阻反向导通绝缘栅双极晶体管及其制造方法。晶体管包括端子结构（200）和有源区（100）。场阻反向导通绝缘栅双极晶体管的底层是N型衬垫，衬垫的背面设置有N型电场停止层（1），电场停止层的一个表面在背衬P型结构（10）的背面设置有背面金属层（12）的背面P型结构（10）的表面。在有源区（100）中形成有从背面P型结构（10）贯穿电场停止层（1）的多个多晶硅填充结构（11）。

59. 发明申请

US20160240528A1 IGBT WITH BUILT-IN DIODE AND MANUFACTURING METHOD THEREFOR 有权
标题翻译：具有内置二极管的IGBT及其制造方法
公开(公告)号：US20160240528A1
公开(公告)日：2016-08-18
申请号：US14901622
申请日：2014-06-09
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Xiaoshe DENG , Shuo ZHANG , Qiang RUI , Genyi WANG
IPC分类号： H01L27/07 , H01L29/739 , H01L29/06 , H01L29/868 , H01L21/8249
CPC分类号： H01L27/0727 , H01L21/8249 , H01L29/0619 , H01L29/0684 , H01L29/0834 , H01L29/402 , H01L29/66333 , H01L29/7395 , H01L29/868
摘要： An insulated gate bipolar translator (IGBT) with a built-in diode and a manufacturing method thereof are provided. The IGBT comprises: a semiconductor substrate (1) of the first conduction type which has a first major surface (1S1) and a second major surface (1S2), wherein the semiconductor substrate (1) comprises an active region (100) and a terminal protection area (200) which is located at the outer side of the active region; an insulated gate transistor unit which is formed at the side of the first major surface (1S1) of the active region (100), wherein a channel of the first conduction type is formed thereon during the conduction thereof; and first semiconductor layers (10) of the first conduction type and second semiconductor layers (11) of the second conduction type of the active region, which are formed at the side of the second major surface (1S2) of the semiconductor substrate (1) alternately, wherein the IGBT only comprises the second semiconductor layers (11) in the terminal protection area (200) which is located at the side of the second major surface (1S2) of the semiconductor substrate (1).
摘要翻译：提供了具有内置二极管的绝缘栅双极转换器（IGBT）及其制造方法。 IGBT包括：具有第一主表面（1S1）和第二主表面（1S2）的第一导电类型的半导体衬底（1），其中半导体衬底（1）包括有源区（100）和端子保护区域（200），其位于有源区域的外侧; 绝缘栅晶体管单元，其形成在有源区（100）的第一主表面（1S1）侧，其中在其导通期间在其上形成第一导电类型的沟道; 以及形成在半导体衬底（1）的第二主表面（1S2）侧的第一导电类型和第二导电类型的有源区的第二半导体层（11）的第一半导体层（10）交替地，其中IGBT仅包括端子保护区域（200）中位于半导体衬底（1）的第二主表面（1S2）侧的第二半导体层（11）。

60. 发明授权

US09343454B2 Electrostatic discharge protection structure and fabrication method thereof 有权
标题翻译：静电放电保护结构及其制造方法
公开(公告)号：US09343454B2
公开(公告)日：2016-05-17
申请号：US14130481
申请日：2013-04-27
申请人： CSMC Technologies Fab1 Co., Ltd.
发明人： Yonghai Hu , Meng Dai , Zhongyu Lin , Guangyang Wang
IPC分类号： H01L29/66 , H01L21/338 , H01L27/02 , H01L29/87 , H01L21/762 , H01L21/8232
CPC分类号： H01L27/0255 , H01L21/0223 , H01L21/02255 , H01L21/26513 , H01L21/32055 , H01L21/76202 , H01L21/76224 , H01L21/8232 , H01L27/0248 , H01L29/402 , H01L29/66121 , H01L29/87
摘要： An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate contact region in the substrate and of the first type of conductivity, well contact region in the well region and of the second type of conductivity, substrate counter-doped region between the substrate contact region and the well contact region and of the second type of conductivity, well counter-doped region between the substrate contact region and the well contact region and of the first type of conductivity, communication region at a lateral junction between the substrate and the well region, first isolation region between the substrate counter-doped region and the communication region, second isolation region between the well counter-doped region and the communication region, oxide layer having one end on the first isolation region and another end on the substrate, and field plate structure on the oxide layer.
摘要翻译：静电放电保护结构包括：第一导电类型的衬底，第二导电类型的阱区，衬底中的衬底接触区域和第一类型的导电性，阱区和第二类型的阱接触区域在衬底接触区域和阱接触区域之间的导电性，衬底反掺杂区域和第二类型的导电性，衬底接触区域和阱接触区域之间的良好的反掺杂区域以及第一类型的导电性，通信在衬底和阱区之间的横向结合处的区域，衬底反掺杂区域和连通区域之间的第一隔离区域，阱对掺杂区域和连通区域之间的第二隔离区域，第一隔离区和衬底上的另一端，以及氧化物层上的场板结构。

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