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51. 发明申请

US20050151261A1 Ultra-high capacitance device based on nanostructures 有权
公开(公告)号：US20050151261A1
公开(公告)日：2005-07-14
申请号：US11044114
申请日：2005-01-26
申请人： Scot Kellar , Sarah Kim
发明人： Scot Kellar , Sarah Kim
IPC分类号： G11C13/02 , H01G4/008 , H01G4/33 , H01L21/02 , H01L21/8242 , H01L27/08 , H01L29/76 , H01L21/4763
CPC分类号： H01L28/84 , B82Y10/00 , G11C13/0033 , G11C13/025 , G11C2213/16 , G11C2213/81 , H01G4/008 , H01G4/33 , H01L27/0805 , H01L27/1085 , Y10S977/70 , Y10S977/72 , Y10S977/721 , Y10S977/723 , Y10S977/902 , Y10S977/963 , Y10T428/24802
摘要： The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.

52. 发明申请

US20050146958A1 Rewrite prevention in a variable resistance memory 有权
标题翻译：在可变电阻存储器中重写防止
公开(公告)号：US20050146958A1
公开(公告)日：2005-07-07
申请号：US11070213
申请日：2005-03-03
申请人： John Moore , R. Baker
发明人： John Moore , R. Baker
IPC分类号： G11C13/00 , G11C8/02 , G11C11/34 , G11C11/406 , G11C11/4091 , G11C13/02 , G11C16/02 , G11C16/28 , G11C7/00
CPC分类号： G11C13/0004 , G11C11/406 , G11C11/4091 , G11C13/0011 , G11C13/003 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C2013/0054 , G11C2207/2281 , G11C2213/72 , G11C2213/76 , G11C2213/79
摘要： A variable resistance memory cell is read by a sense amplifier but without rewriting the contents of the memory cell. If the memory cell has an access transistor, the access transistor is switched off to decouple the cell from the bit line after a predetermined amount of time. The predetermined amount of time is sufficiently long enough to permit the logical state of the cell to be transferred to the bit line and also sufficiently short to isolate the cell from the bit line before the sense amplifier operates. For memory cells which do not utilize an access transistor, an isolation transistor may be placed in the bit line located between and serially connection the portion of the bit line from the sense amplifier to the isolation transistor and the portion of the bit line from the isolation transistor to the memory cell. The isolation transistor, normally conducting, is switched off after the predetermined time past the time the bit line begins to discharge through the memory cell, thereby isolating the memory cell from the sense amplifier before a sensing operation begins.
摘要翻译：可变电阻存储单元由读出放大器读取，但不重写存储单元的内容。如果存储单元具有存取晶体管，则在预定时间量之后，存取晶体管被切断以将单元与位线去耦。预定的时间量足够长以允许将单元的逻辑状态传送到位线，并且还足够短以在读出放大器操作之前将单元与位线隔离。对于不使用存取晶体管的存储单元，可以将隔离晶体管放置在位线之间，位线之间并且将位线的从读出放大器的部分串联连接到隔离晶体管，并且位线的部分与隔离晶体管到存储单元。在通过存储单元的位线开始放电的时间之后的预定时间之后，正常导通的隔离晶体管被关断，从而在感测操作开始之前将存储单元与读出放大器隔离。

53. 发明授权

US06911373B2 Ultra-high capacitance device based on nanostructures 有权
标题翻译：基于纳米结构的超高电容器件
公开(公告)号：US06911373B2
公开(公告)日：2005-06-28
申请号：US10251197
申请日：2002-09-20
申请人： Scot A. Kellar , Sarah E. Kim
发明人： Scot A. Kellar , Sarah E. Kim
IPC分类号： G11C13/02 , H01G4/008 , H01G4/33 , H01L21/02 , H01L21/8242 , H01L27/08 , H01L21/20
CPC分类号： H01L28/84 , B82Y10/00 , G11C13/0033 , G11C13/025 , G11C2213/16 , G11C2213/81 , H01G4/008 , H01G4/33 , H01L27/0805 , H01L27/1085 , Y10S977/70 , Y10S977/72 , Y10S977/721 , Y10S977/723 , Y10S977/902 , Y10S977/963 , Y10T428/24802
摘要： The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric.The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.
摘要翻译：本发明公开了一种提供基板的方法，在衬底上形成下导体; 在下导体上形成导电纳米结构; 在导电纳米结构上形成薄的电介质; 以及在所述薄电介质上形成上导体。本发明还公开了一种包括基板的装置; 位于衬底上方的下导体; 位于下导体上的导电纳米结构; 位于导电纳米结构之上的薄电介质; 以及位于薄电介质上方的上导体。

54. 发明申请

US20050128791A1 Phase change resistor cell and nonvolatile memory device using the same 有权
标题翻译：相变电阻单元和使用其的非易失性存储器件
公开(公告)号：US20050128791A1
公开(公告)日：2005-06-16
申请号：US10879140
申请日：2004-06-30
申请人： Hee Kang
发明人： Hee Kang
IPC分类号： G11C13/02 , G11C16/02 , G11C16/06
CPC分类号： G11C13/0004 , G11C13/003 , G11C13/0033 , G11C14/009 , G11C2213/76
摘要： A nonvolatile memory device features a phase change resistor cell. More specifically, a phase change resistor and a hybrid switch which does not require an additional gate control signal are used to embody rapid nonvolatile SRAM characteristics. In the nonvolatile memory device, a cell plate is connected to a top electrode of a nonvolatile resistor memory device whose resistance state is changed by current values, and the hybrid switch is connected between a flip-flop and a bottom electrode of the nonvolatile resistor memory device, thereby improving characteristics of the rapid nonvolatile memory.
摘要翻译：非易失性存储器件具有相变电阻器单元。更具体地，使用不需要附加的栅极控制信号的相变电阻器和混合开关来体现快速的非易失性SRAM特性。在非易失性存储器件中，单元板连接到电阻状态由电流值改变的非易失性电阻存储器件的顶部电极，并且混合开关连接在触发器和非易失性电阻存储器的底部电极之间器件，从而提高快速非易失性存储器的特性。

55. 发明申请

US20050122781A1 Nonvolatile memory programmable by a heat induced chemical reaction 有权
标题翻译：非易失性存储器可通过热诱导化学反应进行编程
公开(公告)号：US20050122781A1
公开(公告)日：2005-06-09
申请号：US11033895
申请日：2005-01-13
申请人： Hsiang-Lan Lung , Rui-Chen Liu
发明人： Hsiang-Lan Lung , Rui-Chen Liu
IPC分类号： G11C13/02 , G11C17/14 , G11C11/34
CPC分类号： G11C13/0002 , G11C17/14
摘要： A nonvolatile memory cell occupying a minimum chip area is provided with a cell structure that includes two or more base materials being programmable by a heat induced chemical reaction to form a layer or layers of alloy. The formation of alloy results in a change in resistance of the cell structure so that one or more programmed states are determined. A semiconductor memory constructed by a large number of the nonvolatile memory cells can be obtained in a compact manner with simple and as few as possible steps. This process vertically stacked layers, and this semiconductor memory is thus easily to be combined with other integrated circuits on a single chip.
摘要翻译：具有最小芯片面积的非易失性存储单元设置有包括两个或更多个基体材料的单元结构，该基底材料可通过热诱导的化学反应来编程以形成一层或多层合金。合金的形成导致电池结构的电阻变化，从而确定一个或多个编程状态。可以以简单且尽可能少的步骤以紧凑的方式获得由大量非易失性存储单元构成的半导体存储器。该方法垂直层叠，因此该半导体存储器容易与单个芯片上的其他集成电路组合。

56. 发明授权

US06903366B2 Chemically synthesized and assembled electronic devices 失效
标题翻译：化学合成和组装电子器件
公开(公告)号：US06903366B2
公开(公告)日：2005-06-07
申请号：US10699172
申请日：2003-10-31
申请人： James R. Heath , R. Stanley Williams , Philip J. Kuekes
发明人： James R. Heath , R. Stanley Williams , Philip J. Kuekes
IPC分类号： B81B7/04 , B82B1/00 , G01R31/28 , G11C13/02 , H01L21/00 , H01L23/532 , H01L27/10 , H01L29/861 , H01L51/00 , H01L51/05 , H01L51/30 , H01L51/40 , H01L29/06
CPC分类号： H01L27/10 , B82B1/00 , B82Y10/00 , B82Y30/00 , G11C13/0009 , G11C13/0014 , G11C13/02 , G11C2213/72 , G11C2213/77 , G11C2213/81 , H01L51/0595 , Y10S977/704 , Y10S977/705 , Y10S977/936
摘要： A route to the fabrication of electronic devices is provided, in which the devices consist of two crossed wires sandwiching an electrically addressable molecular species. The approach is extremely simple and inexpensive to implement, and scales from wire dimensions of several micrometers down to nanometer-scale dimensions. The device of the present invention can be used to produce crossbar switch arrays, logic devices, memory devices, and communication and signal routing devices. The present invention enables construction of molecular electronic devices on a length scale than can range from micrometers to nanometers via a straightforward and inexpensive chemical assembly procedure. The device is either partially or completely chemically assembled, and the key to the scaling is that the location of the devices on the substrate are defined once the devices have been assembled, not prior to assembly.
摘要翻译：提供了制造电子器件的途径，其中器件由夹着电可寻址分子种类的两条交叉导线组成。该方法实现起来非常简单和便宜，并且从几微米的线尺寸缩小到纳米级尺寸。本发明的装置可用于产生交叉开关阵列，逻辑器件，存储器件以及通信和信号路由器件。本发明能够通过直接且廉价的化学组装程序在长度尺度上构建分子电子器件，其尺寸范围可以从微米到纳米。该装置部分或完全化学地组装，并且缩放的关键在于，一旦装置组装而不是装配之前，基板上的装置的位置被定义。

57. 发明申请

US20050117441A1 Nanoscopic wire-based devices and arrays 审中-公开
标题翻译：纳米线性基于线的器件和阵列
公开(公告)号：US20050117441A1
公开(公告)日：2005-06-02
申请号：US10973665
申请日：2004-10-26
申请人： Charles Lieber , Thomas Rueckes , Ernesto Joselevich , Kevin Kim
发明人： Charles Lieber , Thomas Rueckes , Ernesto Joselevich , Kevin Kim
IPC分类号： B82B1/00 , B82B3/00 , G11C13/02 , G11C23/00 , H01H59/00 , H01L27/10 , H01L27/24 , H01L29/06 , H01L29/66 , H01L49/00 , H01L51/00 , H01L51/30 , G11C11/00
CPC分类号： G11C23/00 , B82Y10/00 , B82Y15/00 , B82Y30/00 , B82Y40/00 , G11C13/025 , G11C2213/16 , G11C2213/72 , G11C2213/77 , G11C2213/81 , H01H1/0094 , H01L27/10 , H01L27/285 , H01L51/0048 , H01L51/0052 , H01L51/0595 , Y10S977/75 , Y10S977/762 , Y10S977/843 , Y10S977/932 , Y10S977/936 , Y10S977/943
摘要： Electrical devices comprised of nanoscopic wires are described, along with methods of their manufacture and use. The nanoscopic wires can be nanotubes, preferably single-walled carbon nanotubes. They can be arranged in crossbar arrays using chemically patterned surfaces for direction, via chemical vapor deposition. Chemical vapor deposition also can be used to form nanotubes in arrays in the presence of directing electric fields, optionally in combination with self-assembled monolayer patterns. Bistable devices are described.
摘要翻译：描述由纳米线组成的电气装置及其制造和使用的方法。纳米线可以是纳米管，优选单壁碳纳米管。它们可以使用化学图案化的表面，通过化学气相沉积方向布置在横杆阵列中。化学气相沉积也可以用于在引导电场的情况下在阵列中形成纳米管，任选地与自组装单层图案组合。描述双稳态设备。

58. 发明授权

US06898098B2 Molecular-junction-nanowire-crossbar-based associative array 有权
标题翻译：分子结 - 纳米线 - 交叉键相关阵列
公开(公告)号：US06898098B2
公开(公告)日：2005-05-24
申请号：US10356027
申请日：2003-01-31
申请人： Greg Snider , Philip J Kuekes
发明人： Greg Snider , Philip J Kuekes
IPC分类号： G11C13/02 , G11C15/00 , G11C15/04
CPC分类号： G11C13/02 , B82Y10/00 , G11C13/0014 , G11C15/00 , G11C15/046 , G11C2213/77 , G11C2213/81 , Y10S977/765
摘要： A method for configuring an associative array within a molecular-junction-nanowire crossbar, and nanoscale associative arrays configured by the method Keys are encoded as field-effect transistors selectively configured within the molecular-junction-nanowire crossbar, and values associated with keys are encoded as diodes selectively configured at molecular-junction-nanowire-crossbar junctions. Keys input into key registers result in a current signal indicating whether or not the key is stored within the associative array as part of a key/value pair and, if stored in the associative array, the value associated with the input key is output.
摘要翻译：用于配置分子结纳米线横截面内的缔合阵列的方法以及通过方法Keys配置的纳米尺度相关阵列被编码为在分子结 - 纳米线交叉开关中有选择地配置的场效应晶体管，并且与键相关的值被编码因为二极管选择性地配置在分子结 - 纳米线 - 交叉点处。输入密钥寄存器的密钥导致当前信号，指示密钥是否作为密钥/值对的一部分存储在关联数组中，并且如果存储在关联数组中，则输出与输入密钥相关联的值。

59. 发明申请

US20050104062A1 SUB-NANOSCALE ELECTRONIC DEVICES AND PROCESSES 失效
标题翻译：子纳米电子器件和工艺
公开(公告)号：US20050104062A1
公开(公告)日：2005-05-19
申请号：US10643747
申请日：2003-08-18
申请人： Mark Reed , James Tour
发明人： Mark Reed , James Tour
IPC分类号： G11C13/02 , G11C13/04 , H01L23/58 , H01L27/02 , H01L29/12 , H01L29/76 , H01L29/88 , H01L51/00 , H01L51/30
CPC分类号： H01L51/0058 , B82Y10/00 , B82Y30/00 , G11C13/0014 , G11C13/0016 , G11C13/02 , G11C13/042 , G11C2213/81 , H01L27/02 , H01L29/7606 , H01L29/882 , H01L51/0036 , H01L51/0052 , H01L51/0062 , H01L51/0067 , H01L51/0068 , H01L51/0094 , H01L51/0595 , H01L2924/0002 , Y10S438/957 , Y10S977/701 , Y10S977/762 , Y10S977/849 , Y10S977/936 , H01L2924/00
摘要： A new class of electronic systems, wherein microelectronic semiconductor integrated circuit devices are integrated on a common substrate with molecular electronic devices.
摘要翻译：一类新的电子系统，其中微电子半导体集成电路器件集成在具有分子电子器件的公共衬底上。

60. 发明申请

US20050100500A1 High-density recording media 审中-公开
标题翻译：高密度记录媒体
公开(公告)号：US20050100500A1
公开(公告)日：2005-05-12
申请号：US10973338
申请日：2004-10-27
申请人： Keisuke Kishita
发明人： Keisuke Kishita
IPC分类号： B82B1/00 , C01B31/02 , G11C13/02 , H01L51/00 , H01L51/30 , D01F9/12
CPC分类号： G11C13/025 , B82Y10/00 , H01L51/0046 , H01L51/0048 , H01L51/0052
摘要： A high-density recording medium comprising a fullerene/carbon nanotube complex (peapod) comprising a single-wall carbon tube in which fullerenes are inserted in series. A structural difference between a locally bound portion and a non-bound portion of the series of fullerenes is recorded as binary information. The limit of storage capacity in conventional recording media based on micrometer-level binarization information recording techniques can be overcome, and a nanoscale binarization information recording technique is provided.
摘要翻译：包含富勒烯/碳纳米管复合物（peapod）的高密度记录介质，其包含富勒烯串联插入的单壁碳管。一系列富勒烯的局部结合部分和非结合部分之间的结构差异被记录为二进制信息。可以克服基于微米级二值化信息记录技术的常规记录介质中的存储容量的限制，并且提供纳米级二值化信息记录技术。

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