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71. 发明授权

US09886239B2 Exponent monitoring 有权
公开(公告)号：US09886239B2
公开(公告)日：2018-02-06
申请号：US14606510
申请日：2015-01-27
申请人： ARM LIMITED
发明人： Guy Larri , Lee Douglas Smith , David Raymond Lutz , Alastair David Reid
IPC分类号： G06F7/48 , G06F7/483 , G06F7/499 , G06F9/30 , G06F17/16 , H03M7/12 , H03M7/24 , G06F11/34 , G06F11/36 , G06F5/01 , G06F7/38 , G06F7/507 , G06F9/38 , G06F7/506
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： A processing apparatus includes floating point arithmetic circuitry coupled to monitoring circuitry. The monitoring circuitry stores exponent limit data indicating at least one of a maximum exponent value and a minimum exponent value processed when performing the floating point arithmetic operations. The monitoring circuitry may be selectively enabled in dependence upon a virtual machine identifier, an application specific identifier or a program counter value range. Exponent limit data may be gathered in respect of different portions of the floating point arithmetic circuitry and/or may be aggregated to form global exponent limit data for the system.

72. 发明授权

US09880811B2 Reproducible stochastic rounding for out of order processors 有权
公开(公告)号：US09880811B2
公开(公告)日：2018-01-30
申请号：US14986991
申请日：2016-01-04
申请人： International Business Machines Corporation
发明人： Jonathan D. Bradbury , Steven R. Carlough , Brian R. Prasky , Eric M. Schwarz
IPC分类号： G06F7/483 , G06F7/58 , G06F17/18 , G06F7/499
CPC分类号： G06F7/483 , G06F7/499 , G06F7/49947 , G06F7/58 , G06F17/18 , G06F2207/483 , G06F2207/58
摘要： A method for generating a random number for use in a stochastic rounding operation is provided. The method includes executing an instruction that causes at least two operands to produce an intermediate result and incrementing a state of a random number generator. The method d further includes causing the random number generator to generate a random number in accordance with the state and producing a final result by utilizing the random number to determine a rounding of the intermediate result.

73. 发明申请

US20170322804A1 Performing Rounding Operations Responsive To An Instruction 审中-公开
公开(公告)号：US20170322804A1
公开(公告)日：2017-11-09
申请号：US15661211
申请日：2017-07-27
申请人： Intel Corporation
发明人： Ronen Zohar , Shane Story
IPC分类号： G06F9/30 , G06F17/10 , G06F7/499
摘要： In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.

74. 发明申请

US20170308357A1 LOGARITHM AND POWER (EXPONENTIATION) COMPUTATIONS USING MODERN COMPUTER ARCHITECTURES 审中-公开
公开(公告)号：US20170308357A1
公开(公告)日：2017-10-26
申请号：US15138846
申请日：2016-04-26
申请人： International Business Machines Corporation
发明人： Konstantinos Bekas , Alessandro Curioni , Yves G. Ineichen , Cristiano Malossi
IPC分类号： G06F7/556 , G06F7/499
CPC分类号： G06F7/556 , G06F7/49915 , G06F2207/5523 , G06F2207/5561
摘要： Embodiments of the present invention may provide the capability to evaluate logarithm and power (exponentiation) functions using either hardware specific instructions, or a hardware specific implementation with reduced memory requirements. An input comprising a floating point representation of a real number may be received and a mantissa and an exponent may be extracted. A function of a logarithm of a mantissa of the real number may be approximated by utilizing a polynomial based on the mantissa. The approximated function of the logarithm may be combined with the exponent for calculating a value comprising a logarithm of the real number. Likewise, an input comprising a floating point representation of a real number and a representation of a second number may be received and an approximation of the real number to the power of the second number may be generated.

75. 发明申请

US20170185379A1 Fused Multiply-Add (FMA) low functional unit 有权
公开(公告)号：US20170185379A1
公开(公告)日：2017-06-29
申请号：US14757942
申请日：2015-12-23
申请人： Intel Corporation
发明人： Cristina S. Anderson , Marius A. Cornea-Hasegan , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Nikita Astafev , Mark J. Charney , Milind B. Girkar , Amit Gradstein , Simon Rubanovich , Zeev Sperber
IPC分类号： G06F7/487 , G06F7/499 , G06F7/485
CPC分类号： G06F7/4876 , G06F7/485 , G06F7/49915
摘要： An example processor includes a register and a fused multiply-add (FMA) low functional unit. The register stores first, second, and third floating point (FP) values. The FMA low functional unit receives a request to perform an FMA low operation: multiplies the first FP value with the second FP value to obtain a first product value; adds the first product with the third FP value to generate a first result value; rounds the first result to generate a first FMA value; multiplies the first FP value with the second FP value to obtain a second product value; adds the second product value with the third FP value to generate a second result value; and subtracts the FMA value from the second result value to obtain a third result value, which can then be normalized and rounded (FMA low result) and sent the FMA low result to an application.

76. 发明授权

US09690543B2 Significance alignment 有权
公开(公告)号：US09690543B2
公开(公告)日：2017-06-27
申请号：US14582974
申请日：2014-12-24
申请人： ARM Limited
发明人： David Raymond Lutz , Neil Burgess , Christopher Neal Hinds
IPC分类号： G06F7/48 , G06F7/483 , G06F7/499 , G06F9/30 , G06F17/16 , H03M7/12 , H03M7/24 , G06F11/34 , G06F11/36 , G06F5/01 , G06F7/38 , G06F7/507 , G06F9/38 , G06F7/506
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： A data processing system uses alignment circuitry to align input operands in accordance with a programmable significance parameter to form aligned input operands. The aligned input operands are supplied to arithmetic circuitry, such as an integer adder or an integer multiplier, where a result value is formed. The result value is stored in an output operand storage element, such as a result register. The programmable significance parameter is independent of the result value.

77. 发明授权

US09645791B2 Multiplier unit with speculative rounding for use with division and square-root operations 有权
公开(公告)号：US09645791B2
公开(公告)日：2017-05-09
申请号：US14305651
申请日：2014-06-16
申请人： Apple Inc.
发明人： Boris S Alvarez-Heredia , Edvin Catovic
IPC分类号： G06F7/544 , G06F7/535 , G06F7/552 , G06F7/499
CPC分类号： G06F7/5443 , G06F7/49936 , G06F7/49947 , G06F7/535 , G06F7/5525 , G06F2207/5355
摘要： Embodiments of a multiplier unit that may be used for division and square root operations are disclosed. The embodiments may provide a reduced and fixed latency for denormalization and rounding used in the division and square root operations. A storage circuit may be configured to receive first and second source operands. A multiplier circuit may be configured to perform a plurality of multiplication operations dependent upon the first and second source operands. Each result after an initial result of the multiplier may also depend on at least one previous result. Circuitry may be configured to perform a shift operation and a rounding operation on a given result of the plurality of results. An error of the given result may be less than a predetermined threshold value.

78. 发明授权

US09639326B2 Floating-point adder circuitry 有权
公开(公告)号：US09639326B2
公开(公告)日：2017-05-02
申请号：US15181747
申请日：2016-06-14
申请人： Altera Corporation
发明人： Tomasz Czajkowski
IPC分类号： G06F7/485 , G06F17/10 , G06F7/499 , G06F5/01
CPC分类号： G06F7/485 , G06F5/012 , G06F7/49915 , G06F17/10 , G06F2207/483
摘要： An integrated circuit is provided that performs floating-point addition or subtraction operations involving at least three floating-point numbers. The floating-point numbers are pre-processed by dynamically extending the number of mantissa bits, determining the floating-point number with the biggest exponent, and shifting the mantissa of the other floating-point numbers to the right. Each extended mantissa has at least twice the number of bits of the mantissa entering the floating-point operation. The exact bit extension is dependent on the number of floating-point numbers to be added. The mantissas of all floating-point numbers with an exponent smaller than the biggest exponent are shifted to the right. The number of right shift bits is dependent on the difference between the biggest exponent and the respective floating-point exponent.

79. 发明授权

US09564187B2 Predicting saturation in a shift operation 有权
标题翻译：预测换档操作中的饱和度
公开(公告)号：US09564187B2
公开(公告)日：2017-02-07
申请号：US14933402
申请日：2015-11-05
申请人： ARM Limited
发明人： David Raymond Lutz , Neil Burgess
IPC分类号： G11C7/00 , G11C7/10 , G06F5/01 , G06F9/30 , G06F7/499
CPC分类号： G11C7/1078 , G06F5/01 , G06F7/49921 , G06F9/30018 , G06F9/30032 , G11C7/1084
摘要： Apparatus for data processing and a method of data processing are provided. Shift circuitry performs a shift operation in response to a shift instruction, shifting bits of an input data value in a direction specified by the shift instruction. Bit location indicator generation circuitry and comparison circuitry operate in parallel with the shift circuitry. The bit location indicator indicates at least one bit location in the input data value which must not have a bit set if the shifted data value is not to saturate. Comparison circuitry compares the bit location indicator with the input data value and indicates a saturation condition if any bits are indicated by the bit position indicator for bit locations which hold set bits in the input data value. A faster indication of the saturation condition thus results.
摘要翻译：提供了数据处理装置和数据处理方法。移位电路响应于移位指令执行移位操作，在由移位指令指定的方向上移位输入数据值的位。位位置指示符生成电路和比较电路与移位电路并行操作。位位置指示符指示输入数据值中的至少一个位位置，如果移位的数据值不饱和，则该位置不能有位置位。比较电路将位位置指示符与输入数据值进行比较，并且如果位位置指示符指示了用于保持输入数据值中的设置位的位位置的任何位，则表示饱和条件。因此，更快地显示饱和条件。

80. 发明授权

US09513871B2 Floating point round-off amount determination processors, methods, systems, and instructions 有权
标题翻译：浮点数四舍五入确定处理器，方法，系统和说明
公开(公告)号：US09513871B2
公开(公告)日：2016-12-06
申请号：US13977257
申请日：2011-12-30
申请人： Cristina S. Anderson , Bret L. Toll , Robert Valentine , Simon Rubanovich , Amit Gradstein
发明人： Cristina S. Anderson , Bret L. Toll , Robert Valentine , Simon Rubanovich , Amit Gradstein
IPC分类号： G06F7/483 , G06F9/30 , G06F7/499
CPC分类号： G06F9/3001 , G06F7/483 , G06F7/49947 , G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30109 , G06F9/3013
摘要： A method of an aspect includes receiving a floating point round-off amount determination instruction. The instruction indicates a source of one or more floating point data elements, indicates a number of fraction bits after a radix point, and indicates a destination storage location. A result including one or more result floating point data elements is stored in the destination storage location in response to the floating point round-off amount determination instruction. Each of the one or more result floating point data elements includes a difference between a corresponding floating point data element of the source in a corresponding position, and a rounded version of the corresponding floating point data element of the source that has been rounded to the indicated number of the fraction bits. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译：一种方面的方法包括接收浮点舍入量确定指令。该指令指示一个或多个浮点数据元素的源，指示小数点之后的小数位数，并指示目的地存储位置。包括一个或多个结果浮点数据元素的结果响应于浮点舍入量确定指令被存储在目的地存储位置中。一个或多个结果浮点数据元素中的每一个包括相应位置的源的相应浮点数据元素与已被舍入到指示的源的相应浮点数据元素的舍入版本之间的差小数位数。公开了其它方法，装置，系统和指令。

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