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    • 71. 发明授权
    • Group III nitride crystal substrate, epilayer-containing group III nitride crystal substrate, semiconductor device and method of manufacturing the same
    • III族氮化物晶体衬底,含有外延层的III族氮化物晶体衬底,半导体器件及其制造方法
    • US08771552B2
    • 2014-07-08
    • US12837872
    • 2010-07-16
    • Keiji IshibashiYusuke Yoshizumi
    • Keiji IshibashiYusuke Yoshizumi
    • H01B1/00
    • C30B23/025C30B29/403C30B33/00H01L29/2003
    • A group III nitride crystal substrate is provided in which a uniform distortion at a surface layer of the crystal substrate represented by a value of |d1 −d2 |/d2 obtained from a plane spacing d1 at the X-ray penetration depth of 0.3 μm and a plane spacing d2 at the X-ray penetration depth of 5 μm is equal to or lower than 1.9 ×10−3, and the main surface has a plane orientation inclined in the direction at an angle equal to or greater than 10° and equal to or smaller than 80° with respect to one of (0001) and (000-1) planes of the crystal substrate. A group III nitride crystal substrate suitable for manufacturing a light emitting device with a blue shift of an emission suppressed, an epilayer-containing group III nitride crystal substrate, a semiconductor device and a method of manufacturing the same can thereby be provided.
    • 提供了一种III族氮化物晶体基板,其中在由X射线穿透深度为0.3μm的平面间距d1获得的| d1 -d2 | / d2的值表示的晶体基板的表面层处的均匀的变形,以及 在5μm的X射线穿透深度处的平面间距d2等于或小于1.9×10 -3,并且主表面具有以等于或大于等于或等于10°的角度在<10-10>方向上倾斜的平面取向 相对于晶体基板的(0001)和(000-1)面之一,比10°等于或小于80°。 因此,可以提供适合于制造抑制发射蓝移的发光器件的III族氮化物晶体衬底,含有外延层的III族氮化物晶体衬底,半导体器件及其制造方法。
    • 77. 发明授权
    • Conducting paste for device level interconnects
    • 用于器件级互连的导电膏
    • US08685284B2
    • 2014-04-01
    • US12884657
    • 2010-09-17
    • Rabindra N. DasRoy H. MagnusonMark D. PoliksVoya R. Markovich
    • Rabindra N. DasRoy H. MagnusonMark D. PoliksVoya R. Markovich
    • H01B1/00H01B1/22H01B1/02
    • H01B1/22H01L2224/81Y10T29/49117
    • A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.
    • 导电糊和形成用于器件级互连的糊的方法。 导电浆料含有80-95%范围内的金属负载,可用于制造五微米器件级互连。 通过混合两种不同的导电浆料制成导电糊料,即使在最终固化后,每个糊料仍将其微量级独立富含区域保持在混合糊料中。 一种糊状物含有至少一种低熔点合金,另一种糊状物含有贵金属填料如金或银薄片。 通常,小于5微米的平均片尺寸适用于五微米互连。 然而,对于5微米互连,优选1微米或更小的银薄片和LMP混合物。 最终混合物中基于LMP的糊剂的量优选为20-50重量%。 纳米微膏实施例显示良好的电收率(81%)和低接触电阻。