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81. 发明申请

US20070194372A1 TRENCH-GATED MOSFET INCLUDING SCHOTTKY DIODE THEREIN 有权
标题翻译：包含肖特基二极管的TRENCH-GFET MOSFET
公开(公告)号：US20070194372A1
公开(公告)日：2007-08-23
申请号：US11740045
申请日：2007-04-25
申请人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L31/00
CPC分类号： H01L29/7813 , H01L29/1095
摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
摘要翻译：公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。

82. 发明申请

US20070001263A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070001263A1
公开(公告)日：2007-01-04
申请号：US11477651
申请日：2006-06-30
申请人： Akio Nakagawa
发明人： Akio Nakagawa
IPC分类号： H01L27/082
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/66348
摘要： A semiconductor device comprises a first semiconductor layer of the first conduction type; and a second semiconductor layer of the second conduction type formed on one surface of the first semiconductor layer. The semiconductor device also comprises a gate electrode formed in a trench with an insulator interposed therebetween, the trench passing through the second semiconductor layer and reaching the first semiconductor layer; and a third semiconductor layer of the first conduction type formed on a surface of the second semiconductor layer between adjacent gate electrodes. The semiconductor device further comprises a first main electrode connected to the second and third semiconductor layers: a fourth semiconductor layer of the second conduction type formed on the other surface of the first semiconductor layer; and a second main electrode connected to the fourth semiconductor layer. The semiconductor layer between adjacent gates has a width d, which satisfies a relation of 2λ≦d≦0.3 μm (λ: a thickness of a channel).
摘要翻译：半导体器件包括第一导电类型的第一半导体层; 以及形成在第一半导体层的一个表面上的第二导电类型的第二半导体层。半导体器件还包括形成在沟槽中的栅电极，绝缘体插入其间，沟槽穿过第二半导体层并到达第一半导体层; 以及形成在相邻栅电极之间的第二半导体层的表面上的第一导电类型的第三半导体层。半导体器件还包括连接到第二和第三半导体层的第一主电极：形成在第一半导体层的另一个表面上的第二导电类型的第四半导体层; 以及连接到第四半导体层的第二主电极。相邻栅极之间的半导体层具有宽度d，其宽度满足2λλ= d <=0.3μm（λ：沟道的厚度）的关系。

83. 发明申请

US20050258479A1 Trench MOSFET 有权
标题翻译：沟槽MOSFET
公开(公告)号：US20050258479A1
公开(公告)日：2005-11-24
申请号：US11127224
申请日：2005-05-12
申请人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/423 , H01L21/336 , H01L21/8234 , H01L27/06 , H01L29/10 , H01L29/41 , H01L29/47 , H01L29/49 , H01L29/78 , H01L29/872 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/1095
摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
摘要翻译：公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。

84. 发明申请

US20050098845A1 Semiconductor device with horizontal MOSFET and schottky barrier diode provided on single substrate 失效
标题翻译：在单个衬底上提供具有水平MOSFET和肖特基势垒二极管的半导体器件
公开(公告)号：US20050098845A1
公开(公告)日：2005-05-12
申请号：US10959201
申请日：2004-10-07
申请人： Tomoko Matsudai , Kazutoshi Nakamura , Akio Nakagawa
发明人： Tomoko Matsudai , Kazutoshi Nakamura , Akio Nakagawa
IPC分类号： H01L29/872 , H01L21/8234 , H01L27/06 , H01L27/07 , H01L29/47 , H01L29/76
CPC分类号： H01L27/0727
摘要： A MOS field-effect transistor includes a semiconductor substrate of a first-conductivity type, a semiconductor layer of the first-conductivity type, a source region of a second-conductivity type, a first drain region of the second-conductivity type, a resurf layer of the second-conductivity type provided in the surface of the semiconductor layer between the source region and the first drain region in contact with the first drain region, and having a lower impurity concentration than the first drain region, a gate insulation film, and a gate electrode provided on the gate insulation film between the source region and resurf layer. A Schottky barrier diode includes a second drain region of the second-conductivity type provided in the surface of the semiconductor layer separate from the first drain region in a direction away from the gate electrode, and a Schottky electrode provided on the semiconductor layer between the first and second drain regions.
摘要翻译： MOS场效应晶体管包括第一导电类型的半导体衬底，第一导电类型的半导体层，第二导电类型的源极区域，第二导电类型的第一漏极区域，第二导电类型的半导体层，所述第二导电型层设置在与所述第一漏极区域接触的所述源极区域和所述第一漏极区域之间的所述半导体层的表面中，并且具有比所述第一漏极区域低的杂质浓度，栅极绝缘膜和栅电极，设置在源极区域和复合层之间的栅极绝缘膜上。肖特基势垒二极管包括设置在半导体层的表面上的第二导电类型的第二漏极区域，该第二漏极区域在远离栅极电极的方向上与第一漏极区域分开，以及肖特基电极，设置在第一和第二漏区。

85. 发明授权

US06878992B2 Vertical-type power MOSFET with a gate formed in a trench 有权
标题翻译：垂直型功率MOSFET，其栅极形成在沟槽中
公开(公告)号：US06878992B2
公开(公告)日：2005-04-12
申请号：US10091423
申请日：2002-03-07
申请人： Yusuke Kawaguchi , Norio Yasuhara , Kazutoshi Nakamura , Akio Nakagawa , Syotaro Ono
发明人： Yusuke Kawaguchi , Norio Yasuhara , Kazutoshi Nakamura , Akio Nakagawa , Syotaro Ono
IPC分类号： H01L21/28 , H01L21/336 , H01L29/41 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66666 , H01L29/42368 , H01L29/7828
摘要： A power MOSFET comprises, between source and drain electrodes, a low resistive semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a high resistive epitaxial layer of the first conductivity type formed on the drift layer, trenches formed to extend from a surface of the epitaxial layer into the drift layer, gate electrodes buried in the trenches with gate insulating films interposed between the gate electrodes and walls of the trenches, low resistive source layers of the first conductivity type formed in a surface region of the epitaxial layer adjacent to the gate insulating films, and a base layer of a second conductivity type formed in the surface region of the epitaxial layer, wherein the epitaxial layer intervening between the trenches is depleted in a case where 0 volt is applied between the source electrode and the gate electrodes.
摘要翻译：功率MOSFET在源极和漏极之间包括第一导电类型的低电阻半导体衬底，形成在半导体衬底上的第一导电类型的漂移层，形成在漂移上的第一导电类型的高电阻外延层形成为从外延层的表面延伸到漂移层中的沟槽，埋入沟槽中的栅电极，栅极绝缘膜插入在栅电极和沟槽的壁之间，形成在第一导电类型的低电阻源层与栅极绝缘膜相邻的外延层的表面区域和形成在外延层的表面区域中的第二导电类型的基极层，其中在0伏特的情况下，介于沟槽之间的外延层被耗尽施加在源电极和栅电极之间。

86. 发明申请

US20050001264A1 Semiconductor device having verical MOS gate structure and method of manufacturing the same 失效
标题翻译：具有真正的MOS栅极结构的半导体器件及其制造方法
公开(公告)号：US20050001264A1
公开(公告)日：2005-01-06
申请号：US10829173
申请日：2004-04-22
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L29/78 , H01L21/3205 , H01L21/336 , H01L29/08 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/76
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933
摘要： A second semiconductor region is formed on a first semiconductor region. A third semiconductor region is formed on a part of the second semiconductor region. A trench ranges from a surface of the third semiconductor region to the third semiconductor region and the second semiconductor region. The trench penetrates the third semiconductor region, and the depth of the trench is shorter than that of a deepest bottom portion of the second semiconductor region, and the second semiconductor region does not exist under a bottom surface of the trench. A gate insulating film is formed on facing side surfaces of the trench. First and second gate electrodes are formed on the gate insulating film. The first and second gate electrodes are separated from each other. The conductive material is formed between the first and second gate electrodes on the side surfaces of the trench, with an insulating film intervened therebetween.
摘要翻译：在第一半导体区域上形成第二半导体区域。在第二半导体区域的一部分上形成第三半导体区域。沟槽的范围从第三半导体区域的表面到第三半导体区域和第二半导体区域。沟槽穿透第三半导体区域，并且沟槽的深度比第二半导体区域的最深底部的深度短，并且第二半导体区域不存在于沟槽的底表面之下。栅极绝缘膜形成在沟槽的相对的侧表面上。在栅极绝缘膜上形成第一和第二栅电极。第一和第二栅电极彼此分离。导电材料形成在沟槽的侧表面上的第一和第二栅电极之间，绝缘膜介于其间。

87. 发明授权

US06740830B2 Trigger switch 失效
标题翻译：触发开关
公开(公告)号：US06740830B2
公开(公告)日：2004-05-25
申请号：US10234175
申请日：2002-09-05
申请人： Takashi Sato , Tetsuzo Nakazawa , Akio Nakagawa , Takaki Tsutsui
发明人： Takashi Sato , Tetsuzo Nakazawa , Akio Nakagawa , Takaki Tsutsui
IPC分类号： H01H1370
CPC分类号： H01H21/24 , H01H2003/326
摘要： A trigger switch includes a trigger member, a rotation detector and a first shaft. The first shaft rotatably supports the trigger member on the rotation detector, so that the rotation detector detects a rotation of the trigger member.
摘要翻译：触发开关包括触发构件，旋转检测器和第一轴。第一轴可旋转地支撑旋转检测器上的触发构件，使得旋转检测器检测触发构件的旋转。

88. 发明授权

US06686613B2 Punch through type power device 有权
标题翻译：打孔式电源设备
公开(公告)号：US06686613B2
公开(公告)日：2004-02-03
申请号：US10383515
申请日：2003-03-10
申请人： Tomoko Matsudai , Hidetaka Hattori , Akio Nakagawa
发明人： Tomoko Matsudai , Hidetaka Hattori , Akio Nakagawa
IPC分类号： H01L29423
CPC分类号： H01L29/7395 , H01L27/0623 , H01L27/1203 , H01L29/0834 , H01L29/0847 , H01L29/1095 , H01L29/42368 , H01L29/42376 , H01L29/66333
摘要： A negative buffer layer and a positive collector layer are formed on a side of one surface of a semiconductor substrate. The positive collector layer is set to have a low dose amount and set shallow so that a low injection efficiency emitter structure is realized. Break down voltage of a power device is controlled by a thickness of a drift layer. A positive base layer, a negative emitter layer and a positive base contact layer are formed on a side of the other surface of the semiconductor substrate. A negative low resistant layer reduces a junction FET effect. An emitter electrode comes into contact with the negative emitter layer and the positive base contact layer. A collector electrode comes into contact with the positive collector layer. A gate electrode is formed on a gate insulating film above a channel region on a surface portion of the positive base layer.
摘要翻译：在半导体衬底的一个表面的一侧上形成负极缓冲层和正极集电极层。正极集电极层被设定为具有低剂量并且设置得较浅，从而实现了低注入效率的发射极结构。功率器件的击穿电压由漂移层的厚度控制。在半导体基板的另一个表面的一侧上形成正基极层，负极发射极层和正极基极接触层。负极低电阻层降低结FET影响。发射极电极与负极发射极层和正极基极接触层接触。集电极与正极集电极层接触。栅极电极形成在阳极基极层的表面部分上的沟道区域上方的栅极绝缘膜上。

89. 发明授权

US06617641B2 High voltage semiconductor device capable of increasing a switching speed 有权
标题翻译：能够提高切换速度的高压半导体装置
公开(公告)号：US06617641B2
公开(公告)日：2003-09-09
申请号：US10059186
申请日：2002-01-31
申请人： Akio Nakagawa , Tomoko Matsudai
发明人： Akio Nakagawa , Tomoko Matsudai
IPC分类号： H01L2976
CPC分类号： H01L29/0834 , H01L29/7397
摘要： An IGBT has a punch-through structure including an n+ buffer layer. It includes a p− low concentration layer formed between the n+ buffer layer and a p+ drain layer. Owing to the low concentration layer, the drain current decreases to zero gradually, not rapidly, when the IGBT is turned off.
摘要翻译： IGBT具有包括n +缓冲层的穿透结构。它包括形成在n +缓冲层和p +漏极层之间的p-低浓度层。由于低浓度层，当IGBT关断时，漏极电流逐渐降低到零，而不会迅速降低。

90. 发明授权

US06614077B2 Semiconductor device improved in ESD reliability 有权
标题翻译：半导体器件提高了ESD可靠性
公开(公告)号：US06614077B2
公开(公告)日：2003-09-02
申请号：US09796427
申请日：2001-03-02
申请人： Kazutoshi Nakamura , Akio Nakagawa , Yusuke Kawaguchi
发明人： Kazutoshi Nakamura , Akio Nakagawa , Yusuke Kawaguchi
IPC分类号： H01L2362
CPC分类号： H01L29/7393 , H01L29/7394 , H01L29/749 , H01L2924/0002 , H01L2924/00
摘要： In an LDMOS, a p+-type anode layer is formed adjacent to an n+-type drain layer. The anode layer makes no contribution to an operation of the LDMOS at a rated voltage and generates holes at the time of ESD. The holes flow into the base layer through the active layer. Electrons flow from a source layer into the drain layer through the active layer. A parasitic thyristor of the LDMOS thus operates, with the result that a source-to-drain holding voltage can be lowered when a large current flows and the current distribution can be uniformed.
摘要翻译：在LDMOS中，与n +型漏极层相邻形成p +型阳极层。阳极层对额定电压下的LDMOS的操作没有贡献，并且在ESD时产生空穴。孔通过活性层流入基层。电子从源极层通过有源层流入漏极层。因此，LDMOS的寄生晶闸管因此工作，结果是当大电流流动并且电流分布可以均匀化时，源极到漏极保持电压可以降低。

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