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    • 4. 发明申请
    • TRENCH-GATED MOSFET INCLUDING SCHOTTKY DIODE THEREIN
    • 包含肖特基二极管的TRENCH-GFET MOSFET
    • US20070194372A1
    • 2007-08-23
    • US11740045
    • 2007-04-25
    • Syotaro OnoAkio NakagawaYusuke KawaguchiYoshihiro Yamaguchi
    • Syotaro OnoAkio NakagawaYusuke KawaguchiYoshihiro Yamaguchi
    • H01L31/00
    • H01L29/7813H01L29/1095
    • Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
    • 公开了一种沟槽MOSFET,其包括:具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层,其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层,其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层,以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层,与p型基底层和金属层接触。
    • 6. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20080251838A1
    • 2008-10-16
    • US12118159
    • 2008-05-09
    • Syotaro OnoYoshihiro YamaguchiYusuke KawaguchiKazutoshi NakamuraNorio YasuharaKenichi MatsushitaShinichi HodamaAkio Nakagawa
    • Syotaro OnoYoshihiro YamaguchiYusuke KawaguchiKazutoshi NakamuraNorio YasuharaKenichi MatsushitaShinichi HodamaAkio Nakagawa
    • H01L29/78
    • H01L29/7802H01L21/26586H01L29/0653H01L29/0696H01L29/0847H01L29/0878H01L29/1095H01L29/402H01L29/407H01L29/42368H01L29/42376H01L29/4238H01L29/66712H01L29/7809
    • A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.
    • 半导体器件包括:半导体衬底,至少其表面部分用作第一导电类型的低电阻漏极层; 连接到所述低电阻漏极层的第一主电极; 形成在低电阻漏极层上的第二导电类型的高电阻外延层; 选择性地形成在高电阻外延层上的第二导电型基极层; 选择性地形成在所述第二导电型基底层的表面部分中的第一导电型源极层; 在由所述第二导电型基底层夹持的区域中形成的沟槽,其深度从所述高电阻外延层的表面延伸到所述半导体衬底; 形成在沟槽的侧壁上的第一导电类型的jfet层; 形成在沟槽中的绝缘层; 形成在第二导电型基底层的表面部分中的第一导电类型的LDD层,以便围绕沟槽的顶面连接到第一导电型jfet层; 控制电极,其形成在所述半导体衬底上,以被分成多个部分,并形成在形成在所述LDD层的一部分表面上的栅极绝缘膜上,所述第一导电型源的端部 并且在由LDD层和第一导电型源极层夹在第二导电型基底层的表面的区域上, 以及与所述第一导电型源极层和所述第二导电型基极欧姆接触以便夹持所述控制电极的第二主电极。
    • 8. 发明授权
    • Trench-gated MOSFET including schottky diode therein
    • 沟槽栅MOSFET,其中包括肖特基二极管
    • US07230297B2
    • 2007-06-12
    • US11127224
    • 2005-05-12
    • Syotaro OnoAkio NakagawaYusuke KawaguchiYoshihiro Yamaguchi
    • Syotaro OnoAkio NakagawaYusuke KawaguchiYoshihiro Yamaguchi
    • H01L29/78
    • H01L29/7813H01L29/1095
    • Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
    • 公开了一种沟槽MOSFET,其包括:具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层,其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层,其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层,以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层,与p型基底层和金属层接触。
    • 10. 发明授权
    • Trench-gated MOSFET including schottky diode therein
    • 沟槽栅MOSFET,其中包括肖特基二极管
    • US07564097B2
    • 2009-07-21
    • US11740045
    • 2007-04-25
    • Syotaro OnoAkio NakagawaYusuke KawaguchiYoshihiro Yamaguchi
    • Syotaro OnoAkio NakagawaYusuke KawaguchiYoshihiro Yamaguchi
    • H01L29/94
    • H01L29/7813H01L29/1095
    • Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
    • 公开了一种沟槽MOSFET,其包括:具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层,其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层,其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层,以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层,与p型基底层和金属层接触。