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1. 发明授权

US08049270B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08049270B2
公开(公告)日：2011-11-01
申请号：US11924175
申请日：2007-10-25
申请人： Miwako Akiyama , Akio Nakagawa , Yusuke Kawaguchi , Syotaro Ono , Yoshihiro Yamaguchi
发明人： Miwako Akiyama , Akio Nakagawa , Yusuke Kawaguchi , Syotaro Ono , Yoshihiro Yamaguchi
IPC分类号： H01L29/732
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/1095 , H01L29/41766
摘要： This semiconductor device an epitaxial layer of a first conductivity type formed on a surface of the first semiconductor layer, and a base layer of a second conductivity type formed on a surface of the epitaxial layer. A diffusion layer of a first conductivity type is selectively formed in the base layer, and a trench penetrates the base layer to reach the epitaxial layer. A gate electrode is formed in the trench through the gate insulator film formed on the inner wall of the trench. A first buried diffusion layer of a second conductivity type is formed in the epitaxial layer deeper than the bottom of the gate electrode. A second buried diffusion layer connects the first buried diffusion layer and the base layer and has a resistance higher than that of the first buried diffusion layer.
摘要翻译：该半导体器件形成在第一半导体层的表面上的第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。在基底层中选择性地形成第一导电类型的扩散层，并且沟槽穿透基底层以到达外延层。通过形成在沟槽内壁上的栅极绝缘膜，在沟槽中形成栅电极。在比栅电极的底部更深的外延层中形成第二导电类型的第一掩埋扩散层。第二掩埋扩散层连接第一掩埋扩散层和基底层，并且具有比第一掩埋扩散层的电阻高的电阻。

2. 发明授权

US07663186B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07663186B2
公开(公告)日：2010-02-16
申请号：US12118159
申请日：2008-05-09
申请人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
发明人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device includes: a substrate, a surface portion thereof serving as a drain layer; a first main electrode connected to the drain layer; an epitaxial layer formed on the drain layer; a base layer formed on the epitaxial layer; a source layer formed in a base layer surface portion; an insulated trench sandwiched by base layers; a JFET layer formed on trench side walls; an LDD layer formed in a base layer surface portion and connected to the JFET layer around a top face of the trench; a control electrode formed on a gate insulating film formed on an LDD layer surface part, on surfaces of source layer end parts facing each other across the trench, and on a base layer region sandwiched by the LDD and source layers; and a second main electrode connected to the source and base layers sandwiching the control electrode.
摘要翻译：半导体器件包括：衬底，用作漏极层的表面部分; 连接到漏极层的第一主电极; 形成在漏极层上的外延层; 形成在外延层上的基底层; 形成在基层表面部分中的源极层; 由基层夹住的绝缘沟槽; 形成在沟槽侧壁上的JFET层; LDD层，其形成在基底表面部分中并且围绕所述沟槽的顶面连接到所述JFET层; 形成在形成在LDD层表面部分上的栅极绝缘膜上的控制电极，在沟槽之间彼此面对的源极层部分的表面上以及由LDD和源极层夹持的基极层区域; 以及连接到夹持控制电极的源极和基极层的第二主电极。

3. 发明授权

US06977414B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06977414B2
公开(公告)日：2005-12-20
申请号：US10460407
申请日：2003-06-13
申请人： Kazutoshi Nakamura , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Syotaro Ono , Akio Nakagawa
发明人： Kazutoshi Nakamura , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Syotaro Ono , Akio Nakagawa
IPC分类号： H01L21/285 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7816 , H01L21/28537 , H01L29/0619 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/4238 , H01L29/7801 , H01L29/7802 , H01L29/7809
摘要： A semiconductor device comprises: a semiconductor layer of a first conductivity type; a pair of base regions of a second conductivity type selectively provided on a surface of the semiconductor layer; and source regions of a first conductivity type, each of the source regions being selectively provided on a surface of each of the base regions. The semiconductor device further comprises an electrical field reducing region of a second conductivity type selectively provided on the surface of the semiconductor layer between the pair of the base regions; a gate insulating film provided on the surface of the base regions; a pair of gate electrodes provided on the gate insulating film, each of the gate electrodes being provided on the surface of the base regions between the source region and the electrical field reducing region; and a source electrode connected to the source regions. The electrical field reducing region is isolated from both of the gate electrode and the source electrode.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 选择性地设置在半导体层的表面上的一对第二导电类型的基极区; 以及第一导电类型的源极区域，每个源区域选择性地设置在每个基极区域的表面上。所述半导体器件还包括选择性地设置在所述一对基极区域之间的所述半导体层的表面上的第二导电类型的电场减小区域; 设置在所述基底区域的表面上的栅极绝缘膜; 设置在所述栅极绝缘膜上的一对栅电极，在所述源极区域和所述电场减少区域之间的所述基极区域的表面上设置各栅极电极; 以及与源极区域连接的源电极。电场减少区域与栅极电极和源极电极隔离。

4. 发明申请

US20070194372A1 TRENCH-GATED MOSFET INCLUDING SCHOTTKY DIODE THEREIN 有权
标题翻译：包含肖特基二极管的TRENCH-GFET MOSFET
公开(公告)号：US20070194372A1
公开(公告)日：2007-08-23
申请号：US11740045
申请日：2007-04-25
申请人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L31/00
CPC分类号： H01L29/7813 , H01L29/1095
摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
摘要翻译：公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。

5. 发明申请

US20050258479A1 Trench MOSFET 有权
标题翻译：沟槽MOSFET
公开(公告)号：US20050258479A1
公开(公告)日：2005-11-24
申请号：US11127224
申请日：2005-05-12
申请人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/423 , H01L21/336 , H01L21/8234 , H01L27/06 , H01L29/10 , H01L29/41 , H01L29/47 , H01L29/49 , H01L29/78 , H01L29/872 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/1095
摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
摘要翻译：公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。

6. 发明申请

US20080251838A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080251838A1
公开(公告)日：2008-10-16
申请号：US12118159
申请日：2008-05-09
申请人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
发明人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.
摘要翻译：半导体器件包括：半导体衬底，至少其表面部分用作第一导电类型的低电阻漏极层; 连接到所述低电阻漏极层的第一主电极; 形成在低电阻漏极层上的第二导电类型的高电阻外延层; 选择性地形成在高电阻外延层上的第二导电型基极层; 选择性地形成在所述第二导电型基底层的表面部分中的第一导电型源极层; 在由所述第二导电型基底层夹持的区域中形成的沟槽，其深度从所述高电阻外延层的表面延伸到所述半导体衬底; 形成在沟槽的侧壁上的第一导电类型的jfet层; 形成在沟槽中的绝缘层; 形成在第二导电型基底层的表面部分中的第一导电类型的LDD层，以便围绕沟槽的顶面连接到第一导电型jfet层; 控制电极，其形成在所述半导体衬底上，以被分成多个部分，并形成在形成在所述LDD层的一部分表面上的栅极绝缘膜上，所述第一导电型源的端部并且在由LDD层和第一导电型源极层夹在第二导电型基底层的表面的区域上，以及与所述第一导电型源极层和所述第二导电型基极欧姆接触以便夹持所述控制电极的第二主电极。

7. 发明申请

US20080035992A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080035992A1
公开(公告)日：2008-02-14
申请号：US11836383
申请日：2007-08-09
申请人： Yusuke KAWAGUCHI , Yoshihiro Yamaguchi , Syotaro Ono , Akio Nakagawa , Miwako Akiyama , Kazuya Nakayama , Masakazu Yamaguchi
发明人： Yusuke KAWAGUCHI , Yoshihiro Yamaguchi , Syotaro Ono , Akio Nakagawa , Miwako Akiyama , Kazuya Nakayama , Masakazu Yamaguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/2815 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/42356 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66734 , H01L29/7828
摘要： This semiconductor device comprises a drift layer of a first conductivity type formed on a drain layer of a first conductivity type, and a drain electrode electrically connected to the drain layer. A semiconductor base layer of a second conductivity type is formed in a surface of the drift layer, and a source region of a first conductivity type is further formed in the semiconductor base layer.A source electrode is electrically connected to the source region and a semiconductor base layer. Plural gate electrodes are formed through a gate insulation film so that a semiconductor base layer may be sandwiched by the gate electrodes. The width of the semiconductor base layer sandwiched by the gate electrodes is 0.3 micrometers or less.
摘要翻译：该半导体器件包括形成在第一导电类型的漏极层上的第一导电类型的漂移层和电连接到漏极层的漏电极。在漂移层的表面上形成第二导电类型的半导体基底层，并且在半导体基底层中进一步形成第一导电类型的源极区。源电极电连接到源区和半导体基层。多个栅电极通过栅极绝缘膜形成，使得半导体基底层可以被栅电极夹持。被栅电极夹持的半导体基底层的宽度为0.3微米以下。

8. 发明授权

US07230297B2 Trench-gated MOSFET including schottky diode therein 有权
标题翻译：沟槽栅MOSFET，其中包括肖特基二极管
公开(公告)号：US07230297B2
公开(公告)日：2007-06-12
申请号：US11127224
申请日：2005-05-12
申请人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/1095
摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
摘要翻译：公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。

9. 发明申请

US20080099837A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080099837A1
公开(公告)日：2008-05-01
申请号：US11924175
申请日：2007-10-25
申请人： Miwako AKIYAMA , Akio Nakagawa , Yusuke Kawaguchi , Syotaro Ono , Yoshihiro Yamaguchi
发明人： Miwako AKIYAMA , Akio Nakagawa , Yusuke Kawaguchi , Syotaro Ono , Yoshihiro Yamaguchi
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/1095 , H01L29/41766
摘要： This semiconductor device an epitaxial layer of a first conductivity type formed on a surface of the first semiconductor layer, and a base layer of a second conductivity type formed on a surface of the epitaxial layer. A diffusion layer of a first conductivity type is selectively formed in the base layer, and a trench penetrates the base layer to reach the epitaxial layer. A gate electrode is formed in the trench through the gate insulator film formed on the inner wall of the trench. A first buried diffusion layer of a second conductivity type is formed in the epitaxial layer deeper than the bottom of the gate electrode. A second buried diffusion layer connects the first buried diffusion layer and the base layer and has a resistance higher than that of the first buried diffusion layer.
摘要翻译：该半导体器件形成在第一半导体层的表面上的第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。在基底层中选择性地形成第一导电类型的扩散层，并且沟槽穿透基底层以到达外延层。通过形成在沟槽内壁上的栅极绝缘膜，在沟槽中形成栅电极。在比栅电极的底部更深的外延层中形成第二导电类型的第一掩埋扩散层。第二掩埋扩散层连接第一掩埋扩散层和基底层，并且具有比第一掩埋扩散层的电阻高的电阻。

10. 发明授权

US07564097B2 Trench-gated MOSFET including schottky diode therein 有权
标题翻译：沟槽栅MOSFET，其中包括肖特基二极管
公开(公告)号：US07564097B2
公开(公告)日：2009-07-21
申请号：US11740045
申请日：2007-04-25
申请人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/1095
摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
摘要翻译：公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。

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