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81. 发明申请

US20150067263A1 SERVICE PROCESSOR PATCH MECHANISM 有权
标题翻译：服务处理器配对机制
公开(公告)号：US20150067263A1
公开(公告)日：2015-03-05
申请号：US14281758
申请日：2014-05-19
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Stephan Gaskins
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F9/3885 , G06F1/04 , G06F1/12 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/30032 , G06F9/30047 , G06F9/30079 , G06F9/30087 , G06F9/30105 , G06F9/30145 , G06F9/3802 , G06F9/3861 , G06F9/4403 , G06F9/4405 , G06F9/4411 , G06F9/4418 , G06F12/0808 , G06F12/084 , G06F12/0875 , G06F13/24 , G06F13/364 , G06F13/42 , G06F21/53 , G06F21/57 , G06F2212/452 , G06F2212/6028 , G06F2212/62 , H01L22/34 , H04L9/0877 , H04L9/0897 , Y02B70/12 , Y02B70/123 , Y02B70/126 , Y02B70/30 , Y02D10/10 , Y02D10/126 , Y02D10/128 , Y02D10/13 , Y02D10/171 , Y02D10/172 , Y02D10/30 , Y02D50/20
摘要： A microprocessor includes a plurality of processing cores, a service processing unit and a memory accessible by both the service processing unit and the plurality of processing cores. At least one of the plurality of processing cores is configured to write a patch to the memory. The patch comprises one or more instructions to be fetched from the memory and executed by the service processing unit after written to the memory by the at least one of the plurality of processing cores.
摘要翻译：微处理器包括多个处理核心，服务处理单元和可由服务处理单元和多个处理核心访问的存储器。多个处理核心中的至少一个被配置为将补丁写入存储器。所述补丁包括要从所述存储器中取出并由所述服务处理单元在由所述多个处理核心中的至少一个写入所述存储器之后执行的一个或多个指令。

82. 发明申请

US20150067215A1 MULTI-CORE SYNCHRONIZATION MECHANISM WITH INTERRUPTS ON SYNC CONDITION 有权
标题翻译：具有同步条件中断的多核同步机制
公开(公告)号：US20150067215A1
公开(公告)日：2015-03-05
申请号：US14281681
申请日：2014-05-19
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F13/24
CPC分类号： G06F9/3885 , G06F1/04 , G06F1/12 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/30032 , G06F9/30047 , G06F9/30079 , G06F9/30087 , G06F9/30105 , G06F9/30145 , G06F9/3802 , G06F9/3861 , G06F9/4403 , G06F9/4405 , G06F9/4411 , G06F9/4418 , G06F12/0808 , G06F12/084 , G06F12/0875 , G06F13/24 , G06F13/364 , G06F13/42 , G06F21/53 , G06F21/57 , G06F2212/452 , G06F2212/6028 , G06F2212/62 , H01L22/34 , H04L9/0877 , H04L9/0897 , Y02B70/12 , Y02B70/123 , Y02B70/126 , Y02B70/30 , Y02D10/10 , Y02D10/126 , Y02D10/128 , Y02D10/13 , Y02D10/171 , Y02D10/172 , Y02D10/30 , Y02D50/20
摘要： A microprocessor includes a plurality of processing cores, each comprising a respective interrupt request input and a control unit configured to receive a respective synchronization request from each of the plurality of processing cores. The control unit is configured to generate an interrupt request to all of the plurality of processing cores on their respective interrupt request inputs in response to detecting that the control unit has received the respective synchronization request from all of the plurality of processing cores.
摘要翻译：微处理器包括多个处理核，每个处理核包括相应的中断请求输入和被配置为从多个处理核中的每一个接收相应的同步请求的控制单元。控制单元被配置为响应于检测到控制单元已经从所有多个处理核心中接收到相应的同步请求而在其各自的中断请求输入端上产生对所有多个处理核心的中断请求。

83. 发明申请

US20150058695A1 CORRECTABLE CONFIGURATION DATA COMPRESSION AND DECOMPRESSION SYSTEM 有权
标题翻译：正确的配置数据压缩和解密系统
公开(公告)号：US20150058695A1
公开(公告)日：2015-02-26
申请号：US13972812
申请日：2013-08-21
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Dinesh K. Jain
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/10 , H03M7/702 , H03M13/05
摘要： An apparatus has a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die, the shared fuse array having a plurality of semiconductor fuses programmed with compressed configuration data and error checking and correction (ECC) codes. The plurality of microprocessor cores is disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores includes a reset controller that is configured to access the compressed configuration data and the ECC codes, to correct errors resulting in corrected compressed configuration data, to decompress all of the corrected compressed configuration data, and to distribute decompressed configuration data to initialize the elements.
摘要翻译：一种装置具有共享熔丝阵列和多个微处理器核心。共享保险丝阵列设置在管芯上，共享保险丝阵列具有多个半导体保险丝，其编程有压缩配置数据和错误校验（ECC）代码。多个微处理器核心设置在管芯上，其中多个微处理器核心中的每一个耦合到共享熔丝阵列，并且被配置为在上电/复位期间访问所有压缩的配置数据，用于初始化多个核心中的每一个。所述多个核心中的每一个包括复位控制器，其被配置为访问所述压缩配置数据和所述ECC代码，以校正导致校正的压缩配置数据的错误，以解压缩所有经校正的压缩配置数据，并且分发解压缩配置数据初始化元素。

84. 发明申请

US20150058564A1 APPARATUS AND METHOD FOR EXTENDED CACHE CORRECTION 审中-公开
标题翻译：扩展高速缓存校正的设备和方法
公开(公告)号：US20150058564A1
公开(公告)日：2015-02-26
申请号：US13972481
申请日：2013-08-21
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Dinesh K. Jain
IPC分类号： G06F12/08 , G06F3/06
CPC分类号： G06F12/0802 , G06F3/0619 , G06F3/0632 , G06F3/0673 , G06F11/1008 , G06F15/76 , G11C29/787 , G11C29/802
摘要： An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The a cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory.
摘要翻译：一种装置包括半导体熔丝阵列，高速缓冲存储器和多个核。半导体熔丝阵列设置在芯片上，其中编程了配置数据。半导体熔丝阵列具有第一多个半导体熔丝，其被配置为存储压缩的高速缓存校正数据。高速缓冲存储器设置在管芯上。多个芯设置在管芯上，其中多个芯中的每个芯耦合到半导体熔丝阵列和高速缓冲存储器，并且被配置为在上电/复位时访问半导体熔丝阵列，以解压缩压缩高速缓存校正数据，并且分发解压缩的缓存校正数据以初始化高速缓冲存储器。

85. 发明申请

US20150055428A1 MICROPROCESSOR MECHANISM FOR DECOMPRESSION OF CACHE CORRECTION DATA 有权
标题翻译：用于解码缓存数据的微处理器机制
公开(公告)号：US20150055428A1
公开(公告)日：2015-02-26
申请号：US13972785
申请日：2013-08-21
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Dinesh K. Jain
IPC分类号： G11C17/16
CPC分类号： G06F12/0875 , G06F1/24 , G06F3/0604 , G06F3/0619 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4403 , G06F9/4405 , G06F9/44505 , G06F11/1008 , G06F11/1068 , G06F12/0646 , G06F12/0692 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1012 , G06F2212/1032 , G06F2212/283 , G06F2212/452 , G06F2212/453 , G06F2212/601 , G06F2212/62 , G06F2212/69 , G11C17/16 , G11C17/18 , G11C29/52 , G11C29/802
摘要： An apparatus has a fuse array, a cache memory, and cores. The fuse array is disposed on a die, into which is programmed the configuration data. The fuse array includes a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores compressed cache correction data. The second plurality of fuses stores compressed fuse correction data that indicates locations and values corresponding to one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The cores are disposed on the die, where each of the cores accesses the fuse array upon power-up/reset. The each of the cores includes a cache fuses decompressor that changes the states according to the locations and the values, decompresses the compressed cache correction data, and distributes decompressed cached correction data to initialize the cache memory.
摘要翻译：一种装置具有熔丝阵列，高速缓冲存储器和核心。熔丝阵列设置在芯片上，其中编程了配置数据。熔丝阵列包括第一多个保险丝和第二多个保险丝。第一组多个保险丝存储压缩缓存校正数据。第二多个保险丝存储压缩的熔丝校正数据，该数据指示与其先前存储的状态将改变其状态的第一组多个保险丝内的一个或多个保险丝对应的位置和值。磁芯设置在芯片上，其中每个磁芯在上电/复位时访问熔丝阵列。每个核心包括高速缓存熔丝解压缩器，其根据位置和值改变状态，解压缩压缩高速缓存校正数据，并分配解压缩的高速缓存校正数据以初始化高速缓冲存储器。

86. 发明授权

US08952734B2 Frequency-control circuits and signal generation devices using the same 有权
标题翻译：频率控制电路和使用其的信号发生装置
公开(公告)号：US08952734B2
公开(公告)日：2015-02-10
申请号：US13850666
申请日：2013-03-26
申请人： Via Technologies, Inc.
发明人： Yeong-Sheng Lee
IPC分类号： H03L7/00 , H03L7/14 , H04L27/00
CPC分类号： H03L7/14 , H03L7/0816 , H03L7/0891 , H03L7/099 , H04L27/00
摘要： A signal generation device is provided to generate an output signal with constant frequency. The signal generation device includes a frequency-control circuit and a voltage-controlled delay line. The frequency-control circuit includes a pulse generator, generating a reference pulse signal according to a transition of the reference signal and a comparison pulse signal according to a transition of the comparison result signal, to re-shape the reference signal and the comparison result signal into narrow pulses suitable for clocking and resetting flip-flops.
摘要翻译：提供信号发生装置以产生具有恒定频率的输出信号。信号发生装置包括频率控制电路和电压控制延迟线。频率控制电路包括脉冲发生器，根据比较结果信号的转变，根据参考信号的转变和比较脉冲信号产生参考脉冲信号，以重新形成参考信号和比较结果信号转换成适合时钟和复位触发器的窄脉冲。

87. 发明申请

US20150012549A1 SORTING METHOD OF DATA DOCUMENTS AND DISPLAY METHOD FOR SORTING LANDMARK DATA 有权
标题翻译：数据文件的分类方法和用于分类LANDMARK数据的显示方法
公开(公告)号：US20150012549A1
公开(公告)日：2015-01-08
申请号：US14271458
申请日：2014-05-07
申请人： VIA Technologies, Inc.
发明人： Guo-Feng Zhang , Yi-Fei Zhu
IPC分类号： G06F17/30
CPC分类号： G06F17/3087 , G06F7/08 , G06F17/30675
摘要： A sorting method of data documents is provided, adapted to an electronic device. The sort method includes the following steps: retrieving a plurality of keywords from contents of a plurality of data documents; retrieving corresponding keyword rankings of the plurality of keywords by a search engine; searching corresponding keyword categories of the plurality of keywords; and generating a sort algorithm based on the plurality of keywords, the keyword ranking and the keyword category of each of the plurality of keywords, and a current ranking of each of the plurality of data documents, wherein the sort algorithm is used to calculate a predicting ranking of another data document and to sort the another data document.
摘要翻译：提供数据文件的分类方法，适用于电子设备。分类方法包括以下步骤：从多个数据文档的内容中检索多个关键字; 通过搜索引擎检索所述多个关键字的对应关键字排名; 搜索所述多个关键字的对应关键词类别; 以及基于所述多个关键词，所述多个关键字中的每一个的关键字排序和关键字类别以及所述多个数据文档中的每一个的当前排名来生成排序算法，其中所述排序算法用于计算预测排序另一个数据文件并排序另一个数据文档。

88. 发明授权

US08911291B2 Display system and display method for video wall 有权
标题翻译：视频墙的显示系统和显示方法
公开(公告)号：US08911291B2
公开(公告)日：2014-12-16
申请号：US13685617
申请日：2012-11-26
申请人： VIA Technologies, Inc.
发明人： Steve Shu Liu
IPC分类号： A63F9/24
CPC分类号： G07F17/3227 , G07F17/3211 , G07F17/3225
摘要： A display system and a display method for video walls are provided. The display system includes at least one server and a plurality of player devices. Each server renders an image and transmits the image to a network. The player devices are coupled to the at least one server through the network. Each player device receives the image or a part of the image rendered by one of the at least one server, and determines a synchronization time together with at least one of the other player devices. Each player device uses a display of a video wall to simultaneously display the image or the part of the image at the synchronization time.
摘要翻译：提供了一种用于视频墙的显示系统和显示方法。显示系统包括至少一个服务器和多个播放器设备。每个服务器呈现图像并将图像传输到网络。播放器设备通过网络耦合到至少一个服务器。每个播放器设备接收图像或由至少一个服务器中的一个呈现的图像的一部分，并且与至少一个其他播放器设备一起确定同步时间。每个播放器设备使用视频墙的显示器在同步时间同时显示图像或图像的一部分。

89. 发明申请

US20140361828A1 DIGITAL POWER GATING WITH PROGRAMMABLE CONTROL PARAMETER 有权
标题翻译：具有可编程控制参数的数字功率增益
公开(公告)号：US20140361828A1
公开(公告)日：2014-12-11
申请号：US14202313
申请日：2014-03-10
申请人： VIA TECHNOLOGIES, INC.
发明人： James R. Lundberg
IPC分类号： H03K17/687
CPC分类号： H03K19/0008
摘要： An integrated circuit including a global supply bus, a gated supply bus, a functional circuit coupled to the gated supply bus, a programmable device that stores a programmed control parameter, and a digital power gating system. The digital power gating system includes gating devices and a power gating control system. Each gating device is coupled between the global and gated supply buses and each has a control terminal. The power gating control system controls a digital control value to control activation of the gating devices. The power gating control system is configured to perform a power gating operation by adjusting the digital control value to control a voltage of the gated supply bus relative to the voltage of the global supply bus. The power gating operation may be adjusted using the programmed control parameter. The programmable device may be a fuse array or a memory programmed with programmed control parameter.
摘要翻译：包括全局电源总线，门控电源总线，耦合到门控电源总线的功能电路，存储编程控制参数的可编程器件和数字电源门控系统的集成电路。数字电源门控系统包括门控设备和电源门控控制系统。每个选通装置耦合在全局和门控供电总线之间，并且每个具有控制终端。电源门控控制系统控制数字控制值以控制门控设备的激活。电源门控控制系统被配置为通过调整数字控制值来执行电力门控操作，以控制门控电源总线相对于全局电源总线的电压的电压。电源门控操作可以使用编程的控制参数进行调整。可编程器件可以是保险丝阵列或用编程控制参数编程的存储器。

90. 发明授权

US08886855B2 Apparatus and method for dynamic alignment of source synchronous bus signals 有权
标题翻译：源同步总线信号动态对准的装置和方法
公开(公告)号：US08886855B2
公开(公告)日：2014-11-11
申请号：US13747140
申请日：2013-01-22
申请人： VIA Technologies, Inc.
发明人： Vanessa S. Canac , James R. Lundberg
IPC分类号： G06F13/00 , G06F17/30 , G06F13/42
CPC分类号： G06F17/30581 , G06F13/4217
摘要： An apparatus that compensates for misalignment on a synchronous data bus. The apparatus includes a replica distribution network, a bit lag control element, and a synchronous lag receiver. The replica distribution network receives a first signal, and generates a second signal, where the replica distribution network comprises replicated propagation characteristics of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive a first one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time.
摘要翻译：补偿同步数据总线上的未对准的装置。该装置包括复制分发网络，位延迟控制元件和同步延迟接收器。复制分发网络接收第一信号，并且生成第二信号，其中复制分发网络包括用于选通的径向分布网络的复制传播特性。比特滞后控制元件被配置为测量从第一信号的断言开始并以第二信号的断言结束的传播时间，并且被配置为在指示传播时间的滞后总线上生成值。同步延迟接收器耦合到位延迟控制元件，并且被配置为接收多个径向分布的选通信号和数据位中的第一个，并被配置为延迟数据位的登记传播时间。

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