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81. 发明授权

US06420748B1 Borderless bitline and wordline DRAM structure 失效
标题翻译：无边界位线和字线DRAM结构
公开(公告)号：US06420748B1
公开(公告)日：2002-07-16
申请号：US09657968
申请日：2000-09-08
申请人： Mark C. Hakey , David V. Horak , William H. Ma , Wendell P. Noble, Jr.
发明人： Mark C. Hakey , David V. Horak , William H. Ma , Wendell P. Noble, Jr.
IPC分类号： H01L27108
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10829 , H01L27/10861 , H01L27/10873 , H01L27/10891
摘要： It is a feature of the present invention that a subminimum dimension wordline links approximately minimum dimensional individual gate segments with the bitline contact being borderless to the wordline. It is still a further object of the present invention to provide a transistor with an individual segment gate conductor and a subminimum dimension gate connector with the bitline contact being borderless to the wordline. A semiconductor structure and method of making same comprising a DRAM cell which has a transistor which includes a gate. The gate comprises an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further comprises a single crystal semiconductor substrate having a source/drain region. An active conductive wordline is deposited on top of and electrically contacting the segment gate conductor with the wordline being a conductive material. Insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. A bitline contact contacting the insulating material surrounds the wordline contact in the source/drain region to thereby make the bitline contact borderless to the wordline.
摘要翻译：本发明的一个特征是，最小尺寸字线连接大致最小尺寸的单独栅极段，位线接触与字线无边界。本发明的另一个目的是提供具有单独的段栅极导体以及具有位线接触对该字线无边界的极小尺寸的栅极连接器。一种半导体结构及其制造方法，其包括具有包括栅极的晶体管的DRAM单元。栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。晶体管还包括具有源/漏区的单晶半导体衬底。活动导电字线沉积在分段栅极导体的顶部并且电接触，其中字线是导电材料。绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。接触绝缘材料的位线接触器围绕源极/漏极区域中的字线触点，从而使位线接触到字线。

82. 发明授权

US06391426B1 High capacitance storage node structures 失效
标题翻译：高电容存储节点结构
公开(公告)号：US06391426B1
公开(公告)日：2002-05-21
申请号：US08878136
申请日：1997-06-19
申请人： Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma
发明人： Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma
IPC分类号： B32B100
CPC分类号： H01L28/82 , G03F7/0045 , G03F7/038 , G03F7/039 , G03F7/095 , H01L21/0274 , H01L21/3085 , Y10S430/168 , Y10T428/24355 , Y10T428/24628
摘要： A high capacitance storage node structure is created in a substrate by patterning a hybrid resist (12) to produce both negative tone (16) and positive tone (18) areas in the exposed region (14). After removal of the positive tone areas (18), the substrate (12) is etched using the unexposed hybrid resist (12) and negative tone area (16) as a mask. This produces a trench (22) in the substrate (12) with a centrally located, upwardly projecting protrusion (24). The capacitor (26) is then created by coating the sidewalls of the trench (22) and protrusion (24) with dielectric (28) and filling the trench with conductive material (30) such as polysilicon.
摘要翻译：通过在混合抗蚀剂（12）中图案化以在曝光区域（14）中产生负色调（16）和正色调（18）区域，在衬底中形成高电容存储节点结构。在去除正色调区域（18）之后，使用未曝光的混合抗蚀剂（12）和负色调区域（16）作为掩模蚀刻衬底（12）。这在基板（12）中产生具有中心定位的向上突出的突起（24）的沟槽（22）。然后通过用电介质（28）涂覆沟槽（22）和突起（24）的侧壁并用诸如多晶硅的导电材料（30）填充沟槽来产生电容器（26）。

83. 发明授权

US06225158B1 Trench storage dynamic random access memory cell with vertical transfer device 失效
标题翻译：沟槽存储动态随机存取存储单元与垂直传输设备
公开(公告)号：US06225158B1
公开(公告)日：2001-05-01
申请号：US09086057
申请日：1998-05-28
申请人： Toshiharu Furukawa , Mark C. Hakey , David V. Horak , William H. Ma , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , David V. Horak , William H. Ma , Jack A. Mandelman
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10891
摘要： A trench storage dynamic random access memory cell with vertical transfer device can be formed in a wafer having prepared shallow trench isolation. Vertical transfer device is built as the deep trenches are formed. Using square printing to form shallow trench isolation and deep trenches, allows for scaling of the cell to very small dimensions.
摘要翻译：可以在具有准备的浅沟槽隔离的晶片中形成具有垂直传输装置的沟槽存储动态随机存取存储器单元。随着形成深沟而建立垂直传输装置。使用方形印刷形成浅沟槽隔离和深沟槽，允许将电池缩放到非常小的尺寸。

84. 发明授权

US06221704B1 Process for fabricating short channel field effect transistor with a highly conductive gate 失效
公开(公告)号：US06221704B1
公开(公告)日：2001-04-24
申请号：US09089650
申请日：1998-06-03
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James S. Nakos , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James S. Nakos , Paul A. Rabidoux
IPC分类号： H01L2144
CPC分类号： H01L21/76897 , H01L21/28123 , H01L21/823842 , H01L29/66575
摘要： Semiconductor devices are fabricated by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a conductive-forming layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the conductive-forming layer; depositing a conductive material through the opening over the conductive layer; planarizing the second insulating layer and the conductive material; removing the second insulating layer, the conductive-forming layer and the first insulating layer except beneath the conductive material; and forming source/drain regions in the substrate; or by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a first conductive-forming layer on the first insulating layer; forming a second conductive layer on the first conductive-forming layer; forming a second insulating layer on the second conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the second conductive layer; depositing a third insulating material through the opening over the conductive layer; planarizing the second insulating layer and the third insulating material; removing the second insulating layer, the first conductive-forming layer and second conductive layer and the first insulating layer except beneath the third insulating material; and forming source/drain regions in the substrate.

85. 发明授权

US06175128B1 Process for building borderless bitline, wordline and DRAM structure and resulting structure 失效
标题翻译：构建无边界位线，字线和DRAM结构以及结构的过程
公开(公告)号：US06175128B1
公开(公告)日：2001-01-16
申请号：US09052538
申请日：1998-03-31
申请人： Mark C. Hakey , David V. Horak , William H. Ma , Wendell P. Noble, Jr.
发明人： Mark C. Hakey , David V. Horak , William H. Ma , Wendell P. Noble, Jr.
IPC分类号： H01L27108
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10829 , H01L27/10861 , H01L27/10873 , H01L27/10891
摘要： It is a feature of the present invention that a subminimum dimension wordline links approximately minimum dimensional individual gate segments with the bitline contact being borderless to the worldline. It is still a further object of the present invention to provide a transistor with an individual segment gate conductor and a subminimum dimension gate connector with the bitline contact being borderless to the wordline. A semiconductor structure and method of making same comprising a DRAM cell which has a transistor which includes a gate. The gate comprises an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further comprises a single crystal semiconductor substrate having a source/drain region. An active conductive wordline is deposited on top of and electrically contacting the segment gate conductor with the wordline being a conductive material. Insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. A bitline contact contacting the insulating material surrounds the wordline contact in the source/drain region to thereby make the bitline contact borderless to the wordline.
摘要翻译：本发明的一个特征是，极小维度字线将大致最小维度单独的门段链接到位线接触与世界线无边界。本发明的另一个目的是提供一种具有单独的段栅极导体和一个极小尺寸的栅极连接器的晶体管，其中位线接触与字线无边界。一种半导体结构及其制造方法，包括具有包括栅极的晶体管的DRAM单元。栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。晶体管还包括具有源/漏区的单晶半导体衬底。活动导电字线沉积在分段栅极导体的顶部并且电接触，其中字线是导电材料。绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。接触绝缘材料的位线接触器围绕源极/漏极区域中的字线触点，从而使位线接触到字线。

86. 发明授权

US5959325A Method for forming cornered images on a substrate and photomask formed thereby 失效
标题翻译：在基板上形成圆角图像的方法和由此形成的光掩模
公开(公告)号：US5959325A
公开(公告)日：1999-09-28
申请号：US917009
申请日：1997-08-21
申请人： William J. Adair , Richard A. Ferguson , Mark C. Hakey , Steven J. Holmes , David V. Horak , Robert K. Leidy , William Hsioh-Lien Ma , Ronald M. Martino , Song Peng
发明人： William J. Adair , Richard A. Ferguson , Mark C. Hakey , Steven J. Holmes , David V. Horak , Robert K. Leidy , William Hsioh-Lien Ma , Ronald M. Martino , Song Peng
IPC分类号： H01L21/033 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L21/0332 , H01L21/0334 , Y10S438/942
摘要： A method for forming square shape images in a lithographic process is disclosed wherein a first plurality of lines running in a first direction is defined in a first, usually sacrificial, layer, and then a second resist is defined wherein the lines run in an intersecting pattern to those of the first layer, thereby creating cornered images wherever the first and second layer intersect and in the open areas between the lines. Methods are proposed for developing the square intersecting areas and the square angle areas defined by the openings. Additionally, a photomask is disclosed in which the length and width of the cornered images are independently patterned using the two-exposure process.
摘要翻译：公开了一种在光刻工艺中形成正方形形状图像的方法，其中沿第一方向延伸的第一多条线被限定在第一，通常是牺牲层中，然后定义第二抗蚀剂，其中线以相交图案到第一层的那些，从而在第一和第二层交叉的任何地方以及在线之间的开放区域中产生拐角图像。提出了用于显影方形交叉区域和由开口限定的方角区域的方法。此外，公开了一种光掩模，其中使用双曝光工艺独立地对角形图像的长度和宽度进行图案化。

87. 发明授权

US5945707A DRAM cell with grooved transfer device 失效
标题翻译：具有槽式转移装置的DRAM单元
公开(公告)号：US5945707A
公开(公告)日：1999-08-31
申请号：US56903
申请日：1998-04-07
申请人： Gary B. Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Jack A. Mandelman , Paul A. Rabidoux
发明人： Gary B. Bronner , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Jack A. Mandelman , Paul A. Rabidoux
IPC分类号： H01L21/8242 , H01L29/72
CPC分类号： H01L27/10876 , H01L27/10861 , H01L27/10891
摘要： A memory cell having a grooved gate formed in a sub-lithographic groove, and methods of making thereof are disclosed. The groove extends the channel length to include the groove sidewalls and width of the groove. Sidewall sections of the channel located along the gate sidewalls have a larger length than the bottom channel section length located along the gate bottom width. Thus, the memory device is primarily controlled by the sidewall channel sections, instead of the bottom channel section. The groove may be a stepped groove formed by a two step etch to further increase the channel length and may be formed centered along the gate conductor width.
摘要翻译：公开了一种在副光刻槽中形成有槽栅的存储单元及其制造方法。凹槽延伸通道长度以包括凹槽侧壁和凹槽的宽度。沿着栅极侧壁的通道的侧壁部分具有比沿着栅极底部宽度定位的底部通道部分长度更大的长度。因此，存储器件主要由侧壁通道部分而不是底部通道部分控制。沟槽可以是通过两步蚀刻形成的阶梯槽，以进一步增加沟道长度，并且可以沿着栅极导体宽度形成为中心。

88. 发明授权

US08512458B2 Chemical and particulate filters containing chemically modified carbon nanotube structures 失效
标题翻译：包含化学改性碳纳米管结构的化学和微粒过滤器
公开(公告)号：US08512458B2
公开(公告)日：2013-08-20
申请号：US12166865
申请日：2008-07-02
申请人： Steven J. Holmes , Mark C. Hakey , David V. Horak , James G. Ryan
发明人： Steven J. Holmes , Mark C. Hakey , David V. Horak , James G. Ryan
IPC分类号： B01D53/02 , B01D59/26 , B01D24/00 , B01D39/14 , D01C5/00 , D01F9/12
CPC分类号： B01D53/02 , B01D2253/102 , B01D2253/304 , B01J20/20 , B01J20/205 , B01J20/3242 , B82Y30/00 , Y10S55/05 , Y10S977/742 , Y10S977/745 , Y10S977/748 , Y10S977/75 , Y10S977/752
摘要： A carbon nanotube filter, a use for a carbon nanotube filter and a method of forming a carbon nanotube filter. The method including (a) providing a carbon source and a carbon nanotube catalyst; (b) growing carbon nanotubes by reacting the carbon source with the nanotube catalyst; (c) forming chemically active carbon nanotubes by forming a chemically active layer on the carbon nanotubes or forming chemically reactive groups on sidewalls of the carbon nanotubes; and (d) placing the chemically active nanotubes in a filter housing.
摘要翻译：碳纳米管过滤器，碳纳米管过滤器的用途和形成碳纳米管过滤器的方法。该方法包括（a）提供碳源和碳纳米管催化剂; （b）使碳源与纳米管催化剂反应生长碳纳米管; （c）通过在碳纳米管上形成化学活性层或在碳纳米管的侧壁上形成化学反应性基团形成化学活性碳纳米管; 和（d）将化学活性纳米管放置在过滤器壳体中。

89. 发明授权

US07932549B2 Carbon nanotube conductor for trench capacitors 有权
标题翻译：碳纳米管导体用于沟槽电容器
公开(公告)号：US07932549B2
公开(公告)日：2011-04-26
申请号：US10596022
申请日：2003-12-18
申请人： Steven J. Holmes , Toshiharu Furukawa , Mark C. Hakey , David V. Horak , Charles W. Koburger, III , Larry A. Nesbit
发明人： Steven J. Holmes , Toshiharu Furukawa , Mark C. Hakey , David V. Horak , Charles W. Koburger, III , Larry A. Nesbit
IPC分类号： H01L27/108
CPC分类号： H01L27/10864 , B82Y10/00 , H01L27/10861 , Y10S977/936 , Y10S977/943 , Y10S977/948
摘要： A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.
摘要翻译：沟槽式存储装置包括在衬底（100）中的沟槽，具有衬在沟槽上的碳纳米管（202）的束和填充沟槽的沟槽导体（300）。可以在碳纳米管和沟槽的侧壁之间形成沟槽电介质（200）。碳纳米管束形成在沟槽内衬的开放圆筒结构。该器件通过在衬底上提供碳纳米管催化剂结构并对衬底中的沟槽进行图案化而形成; 然后将碳纳米管向下生长到沟槽中以与碳纳米管束对准沟槽，然后用沟槽导体填充沟槽。

90. 发明授权

US07889317B2 Immersion lithography with equalized pressure on at least projection optics component and wafer 有权
标题翻译：至少在投影光学部件和晶片上具有均衡压力的浸没光刻
公开(公告)号：US07889317B2
公开(公告)日：2011-02-15
申请号：US12051572
申请日：2008-03-19
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Peter H. Mitchell
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Peter H. Mitchell
IPC分类号： G03B27/42
CPC分类号： G03F7/70341
摘要： An immersion lithography apparatus and method, and a lithographic optical column structure are disclosed for conducting immersion lithography with at least the projection optics of the optical system and the wafer in different fluids at the same pressure. In particular, an immersion lithography apparatus is provided in which a supercritical fluid is introduced about the wafer, and another fluid, e.g., an inert gas, is introduced to at least the projection optics of the optical system at the same pressure to alleviate the need for a special lens. In addition, the invention includes an immersion lithography apparatus including a chamber filled with a supercritical immersion fluid and enclosing a wafer to be exposed and at least a projection optic component of the optical system.
摘要翻译：公开了一种浸没式光刻设备和方法以及平版印刷光学柱结构，用于在相同压力下用不同流体中的光学系统和晶片的至少投影光学器件进行浸没光刻。特别地，提供了一种浸没式光刻设备，其中超临界流体被引入晶片周围，并且另一种流体（例如惰性气体）在相同的压力下被引入光学系统的至少投影光学器件以减轻需要用于特殊镜头。此外，本发明包括浸没式光刻设备，其包括填充有超临界浸没流体的腔室并且封装要暴露的晶片和至少光学系统的投影光学部件。

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