专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20160336952A1 Method and Apparatus for Reducing SAR Input Loading 有权
标题翻译：减少SAR输入负载的方法和装置
公开(公告)号：US20160336952A1
公开(公告)日：2016-11-17
申请号：US15206433
申请日：2016-07-11
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Raghu Nandan Srinivasa , Tharun Nagulu
IPC分类号： H03M1/12 , G06F1/32 , G06F13/40 , H03M1/38 , H03M1/46
CPC分类号： H03M1/124 , G06F1/3287 , G06F13/4022 , H03M1/00 , H03M1/12 , H03M1/1245 , H03M1/38 , H03M1/466 , H03M1/468 , H03M1/804
摘要： The disclosure provides a successive approximation register analog to digital converter (SAR ADC). The SAR ADC includes a charge sharing DAC that includes an array of MSB (most significant bit) capacitors, an array of LSB (least significant bit) capacitors, and an error correction capacitor. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A successive approximation register (SAR) state machine is coupled to the zero crossing detector and operates the charge sharing DAC in a sampling mode and a conversion mode. During the sampling mode an input voltage is provided to the array of MSB capacitors and the error correction capacitor.
摘要翻译：本公开提供了逐次逼近寄存器模数转换器（SAR ADC）。 SAR ADC包括一个电荷共享DAC，包括一个MSB（最高有效位）电容阵列，一个LSB（最低有效位）电容器阵列和一个纠错电容器。零交叉检测器耦合到电荷共享DAC。过零检测器产生数字输出。逐次逼近寄存器（SAR）状态机耦合到过零检测器，并以采样模式和转换模式操作电荷共享DAC。在采样模式期间，向MSB电容器阵列和纠错电容器提供输入电压。

82. 发明申请

US20160327967A1 MIXED MODE COMPENSATION CIRCUIT 审中-公开
公开(公告)号：US20160327967A1
公开(公告)日：2016-11-10
申请号：US15201440
申请日：2016-07-02
申请人： RICHTEK TECHNOLOGY CORPORATION
发明人： Chien-Fu Tang , Jiun-Hung Pan , Isaac Y. Chen
IPC分类号： G05F1/10 , H03M1/38
CPC分类号： G05F1/10 , H02M3/157 , H02M2001/0025 , H03M1/38
摘要： A mixed mode compensation circuit for a power converter generate a digital signal according to a reference signal and a feedback signal which is related to the output voltage of the power converter, convert the digital signal into a first analog signal, offset the first analog signal with a variable offset value to generate a second analog signal, and filter out high-frequency components of the second analog signal to generate a third analog signal for stable output voltage of the power converter. The mixed mode compensation does not require large capacitors, and thus the circuit can be integrated into an integrated circuit.

83. 发明申请

US20160305988A1 DIGITALLY ASSISTED CURRENT SENSE CIRCUIT AND METHOD FOR DIGITIZING A SENSED SIGNAL 审中-公开
标题翻译：数字化辅助电流检测电路和用于数字化感测信号的方法
公开(公告)号：US20160305988A1
公开(公告)日：2016-10-20
申请号：US15099710
申请日：2016-04-15
申请人： ZENTRUM MIKROELEKTRONIK DRESDEN AG
发明人： David STACK
IPC分类号： G01R19/25 , G01R19/257 , H02M3/158 , H03M1/38 , H02M3/157
CPC分类号： G01R19/2506 , G01R19/257 , H02M3/157 , H02M3/158 , H03M1/361 , H03M1/38 , H03M1/462
摘要： A method for digitizing a sensed signal in a digitally assisted current sense circuit and a digitally assisted current sense circuit that uses the disclosed method realize a simple way to sense and convert an analogue current signal into a digital signal. The method includes the steps of generating a voltage corresponding to a sensed inductor current IL; and amplifying and buffering the voltage for creating an input signal to be converted by an analogue-to-digital converter (ADC). The ADC uses an estimate of the inductor current provided by a modified digital observer circuit as a starting point for an analogue-to-digital conversion.
摘要翻译：在数字辅助电流检测电路中数字化感测信号的方法和使用所公开方法的数字辅助电流检测电路实现了将模拟电流信号转换成数字信号的简单方法。该方法包括产生对应于感测的电感器电流IL的电压的步骤; 以及放大和缓冲用于产生由模拟 - 数字转换器（ADC）转换的输入信号的电压。 ADC使用由修改的数字观察器电路提供的电感电流的估计作为模数转换的起始点。

84. 发明授权

US09455046B2 Adaptive analog-to-digital conversion based on signal prediction 有权
标题翻译：基于信号预测的自适应模数转换
公开(公告)号：US09455046B2
公开(公告)日：2016-09-27
申请号：US14605835
申请日：2015-01-26
申请人： 9011579 CANADA INCORPOREE
发明人： Masum Hossain , Maruf H. Mohammad
IPC分类号： H04L7/00 , G11C27/02 , H03L5/00 , G05F1/10 , H03M1/38 , H03M1/12 , H04L7/033 , H04L25/03
CPC分类号： H03M1/002 , G05F1/10 , G11C27/02 , H03L7/0807 , H03M1/124 , H03M1/1245 , H03M1/1255 , H03M1/361 , H03M1/38 , H04L7/0087 , H04L7/033 , H04L7/0332 , H04L7/0334 , H04L25/03006 , H04L25/06
摘要： Methods and apparatuses are described for performing adaptive analog-to-digital conversion and time-to-delay conversion by using signal prediction to adjust reference voltages of adjustable comparators.
摘要翻译：描述了通过使用信号预测来调节可调比较器的参考电压来执行自适应模数转换和时间到延迟转换的方法和装置。

85. 发明授权

US09385740B2 SAR ADC and method thereof 有权
标题翻译： SAR ADC及其方法
公开(公告)号：US09385740B2
公开(公告)日：2016-07-05
申请号：US14919830
申请日：2015-10-22
申请人： MEDIATEK Inc.
发明人： Chi Yun Wang , Jen-Che Tsai , Shu-Wei Chu
IPC分类号： H03M1/38 , H03M1/46 , H03M1/42 , H03M1/12 , H03M1/08 , H03M1/40
CPC分类号： H03M1/462 , H03M1/0854 , H03M1/12 , H03M1/1245 , H03M1/38 , H03M1/403 , H03M1/42 , H03M1/466 , H03M1/468 , H03M3/37 , H03M3/458
摘要： A SAR ADC including a comparator, an input switch unit, a positive conversion capacitor array, a negative conversion capacitor array, and a SAR controller is provided. The input switch unit alternately couples and decouples a differential analog input signal to the comparator. The positive and negative conversion capacitor arrays sample the differential analog input signal during the sampling phase. The SAR controller resets the switches in the capacitor arrays at the end of the sampling phase to change the sampled voltage into a residual signal, generates an intermediate digital code to control the switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generates the digital code according to the intermediate digital code, and uses an inverted intermediate digital code to control the switches at the end of the conversion phase.
摘要翻译：提供了包括比较器，输入开关单元，正转换电容器阵列，负转换电容器阵列和SAR控制器的SAR ADC。输入开关单元将差分模拟输入信号交替耦合到比较器。正和负转换电容器阵列在采样阶段对差分模拟输入信号进行采样。 SAR控制器在采样阶段结束时复位电容器阵列中的开关，将采样电压改变为残余信号，产生一个中间数字代码，根据比较器的输出在转换阶段控制开关，以转换到中间数字码的残留信号，根据中间数字码产生数字码，并在转换阶段结束时使用反相中间数字码来控制开关。

86. 发明申请

US20160191071A1 METHOD AND APPARATUS FOR CALIBRATION OF A TIME INTERLEAVED ADC 有权
标题翻译：用于校准时间间隔ADC的方法和装置
公开(公告)号：US20160191071A1
公开(公告)日：2016-06-30
申请号：US14858793
申请日：2015-09-18
申请人： Luxtera, Inc.
发明人： Josephus Van Engelen , Aaron Buchwald , Ralph Duncan
IPC分类号： H03M1/38 , H03M1/12 , H03M1/06
CPC分类号： H03M1/38 , H03M1/0675 , H03M1/0678 , H03M1/0836 , H03M1/1215 , H03M1/124 , H03M1/14
摘要： A system for calibrating time interleaved ADCs is disclosed and may include a time interleaved analog-to-digital converter (ADC) for converting analog signals to digital signals, the time interleaved ADC comprising: a plurality of active slices, and a plurality of reference slices, each reference slice associated with a corresponding one of the plurality of active slices. An output of each reference slice may be used to correct distortion in an output of the corresponding active slice. Each active slice may sample an input signal at a first rate and each associated reference slice may sample the input signal at a second rate, the second rate being slower than the first rate. Each sample taken by one of the plurality of reference slices may then be taken concurrent with a sample taken by the associated active slice. Each reference slice may include a reference sampling module and a dummy load.
摘要翻译：公开了一种用于校准时间交错ADC的系统，并且可以包括用于将模拟信号转换为数字信号的时间交织模数转换器（ADC），所述时间交织ADC包括：多个活动切片和多个参考切片，每个参考切片与所述多个活动切片中的对应的一个相关联。可以使用每个参考片的输出来校正相应活动片的输出中的失真。每个活动切片可以以第一速率对输入信号进行采样，并且每个相关联的参考切片可以以第二速率对输入信号进行采样，第二速率比第一速率慢。然后可以将多个参考切片中的一个采样的每个采样与由相关联的活动切片采集的采样同时进行。每个参考切片可以包括参考采样模块和虚拟负载。

87. 发明授权

US09337859B2 Method and system for asynchronous successive approximation analog-to-digital convertor (ADC) architecture 有权
标题翻译：用于异步逐次逼近模数转换器（ADC）架构的方法和系统
公开(公告)号：US09337859B2
公开(公告)日：2016-05-10
申请号：US14812327
申请日：2015-07-29
申请人： MaxLinear, Inc.
发明人： Xuefeng Chen , Kok Lim Chan , Eric Fogleman , Sheng Ye
IPC分类号： H03M1/10 , H03M1/38 , H03M1/06 , H03M1/12 , H03M1/46
CPC分类号： H03M1/38 , H03M1/06 , H03M1/0682 , H03M1/125 , H03M1/466
摘要： Methods and systems are provided for controlling signal processing outputs. In signal processing circuitry, searching through a plurality of quantization levels for a quantization level that matches an analog input, and when the search fails within a particular amount of time, adjusting at least a portion of an output of the signal processing circuitry. The adjusting comprises setting the at least portion of the output to a predefined value. Setting the output, or portions thereof, may comprise selecting between output of a normal processing path and output of a code generation path configured for handling search failures. Timing information may be generated for use in controlling generating of the output of the signal processing circuitry. The timing information may be used in measuring per-cycle operation time during the search through the plurality of quantization levels.
摘要翻译：提供了用于控制信号处理输出的方法和系统。在信号处理电路中，通过多个量化级别搜索与模拟输入匹配的量化级别，以及当在特定时间量内搜索失败时，调整信号处理电路的输出的至少一部分。调整包括将输出的至少部分设置为预定值。设置输出或其部分可以包括在正常处理路径的输出和被配置用于处理搜索失败的代码生成路径的输出之间进行选择。可以产生用于控制信号处理电路的输出的产生的定时信息。定时信息可以用于在通过多个量化级别的搜索期间测量每周期操作时间。

88. 发明申请

US20160126966A1 Successive approximation analog-to-digital converter and conversion method 有权
标题翻译：逐次逼近模数转换器和转换方法
公开(公告)号：US20160126966A1
公开(公告)日：2016-05-05
申请号：US14876695
申请日：2015-10-06
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： SHIH-HSIUNG HUANG
IPC分类号： H03M1/00 , H03M1/38 , H03M1/12 , G04F10/00
CPC分类号： H03M1/002 , G04F10/005 , H03M1/1245 , H03M1/145 , H03M1/20 , H03M1/38
摘要： The present invention discloses a successive approximation analog-to-digital converter capable of improving the accuracy of analog-to-digital conversion. An embodiment of this converter comprises: a successive approximation analog-to-digital converting circuit operable to generate M bits according to an analog input signal in which the M bits include a most significant bit (MSB) and successive M−1 bit(s) in succession to the MSB while the number M is an integer greater than one; and a multi-bit generating circuit operable to receive a capacitor array output signal and a comparison signal outputted from the successive approximation analog-to-digital converting circuit for a predetermined time after the generation of the M bits, and then generate N bits at a time accordingly in which the N bits include a least significant bit (LSB) and successive N−1 bit(s) ahead of the LSB while the number N is an integer greater than one.
摘要翻译：本发明公开了一种能够提高模数转换精度的逐次逼近模数转换器。该转换器的实施例包括：逐次逼近模数转换电路，用于根据M位包括最高有效位（MSB）和连续M-1位的模拟输入信号产生M位，数字M是大于1的整数; 以及多位产生电路，用于在生成M位之后的预定时间内接收从逐次逼近模数转换电路输出的电容器阵列输出信号和比较信号，然后在时间，其中N位包括LSB之前的最低有效位（LSB）和连续N-1位，而数字N是大于1的整数。

89. 发明授权

US09312840B2 LC lattice delay line for high-speed ADC applications 有权
标题翻译：用于高速ADC应用的LC晶格延迟线
公开(公告)号：US09312840B2
公开(公告)日：2016-04-12
申请号：US14194107
申请日：2014-02-28
申请人： ANALOG DEVICES TECHNOLOGY
发明人： Yunzhi Dong , Zhao Li , Richard E. Schreier , Hajime Shibata , Trevor Clifford Caldwell
IPC分类号： H03M1/38 , H03K5/159 , H03M1/14 , H03M1/06 , H03M3/00
CPC分类号： H03K5/159 , H03M1/0626 , H03M1/14 , H03M1/145 , H03M1/38 , H03M3/414 , H03M3/464
摘要： This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.
摘要翻译：本公开描述了使用被动连续时间（CT）延迟线用于高速CT模数转换器（ADC）应用的技术和方法。在这些CT ADC通用的连续时间残留产生阶段，模拟输入和DAC输出之间的适当延迟至关重要。具体来说，使用电感 - 电容（LC）晶格延迟元件来实现高性能CT流水线ADC和CT delta-sigma（＆Dgr＆amp; Sgr）ADC。使用基于LC晶格的延迟元件为具有良好控制的阻抗的连续时间信号提供宽带群延迟。这将是构建高性能CT ADC的重要电路元件，特别是在需要CT信号与其数字化版本之间产生低噪声和低失真残差的架构中。基于LC晶格的延迟元件实现了高速连续时间流水线ADC和Δ-ΣADC所需的无噪声，无失真的宽带延迟。

90. 发明申请

US20160053705A1 SEMICONDUCTOR DEVICE, ANALOG-TO-DIGITAL CONVERSION METHOD, ONBOARD SYSTEM, AND MEASUREMENT METHOD 审中-公开
标题翻译：半导体器件，模拟数字转换方法，板上系统和测量方法
公开(公告)号：US20160053705A1
公开(公告)日：2016-02-25
申请号：US14827287
申请日：2015-08-15
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Masashi GOTO
IPC分类号： F02D41/26 , H03M1/00 , F02D41/30 , H03M1/38 , G01R19/257 , G07C5/02 , G06G7/18 , H03M1/12
CPC分类号： F02D41/263 , F02D41/30 , G01R19/257 , H03M1/002 , H03M1/1225 , H03M1/1245 , H03M1/181 , H03M1/52
摘要： There is provided a semiconductor device including: an integrator that repeats integrating a first reference voltage after integrating an analog signal; a comparator that compares an output of the integrator and a second reference voltage; a counter circuit that counts a first integration time determined to integrate the analog signal, and a second integration time until the output of the integrator reaches the second reference voltage from start of integration of the first reference voltage; a calculation circuit that calculates a digital value of the analog signal based on the first and the second integration times; a control circuit that performs control so that the analog signal is input to the integrator while the counter circuit counts the first integration time; and an integration time update circuit that updates the first integration time counted by the counter circuit based on the second integration time counted thereby.
摘要翻译：提供了一种半导体器件，包括：积分器，其在对模拟信号进行积分之后重复积分第一参考电压; 比较器，用于比较积分器的输出和第二参考电压; 计数电路，其计算确定为积分模拟信号的第一积分时间，以及第二积分时间，直到积分器的输出从第一参考电压的积分开始到达第二参考电压; 计算电路，其基于第一和第二积分时间计算模拟信号的数字值; 控制电路，当所述计数器电路对所述第一积分时间进行计数时，进行所述模拟信号输入到所述积分器的控制; 以及积分时间更新电路，其基于由此计数的第二积分时间来更新由计数器电路计数的第一积分时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式