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1. 发明授权

US09054130B2 Bottle-neck recess in a semiconductor device 有权
标题翻译：半导体器件中的瓶颈凹槽
公开(公告)号：US09054130B2
公开(公告)日：2015-06-09
申请号：US12841763
申请日：2010-07-22
申请人： Eric Peng , Chao-Cheng Chen , Ming-Hua Yu , Ying Hao Hsieh , Tze-Liang Lee , Chii-Horng Li , Syun-Ming Jang , Shih-Hao Lo
发明人： Eric Peng , Chao-Cheng Chen , Ming-Hua Yu , Ying Hao Hsieh , Tze-Liang Lee , Chii-Horng Li , Syun-Ming Jang , Shih-Hao Lo
IPC分类号： H01L21/302 , H01L29/66 , H01L21/306 , H01L21/3065 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/30608 , H01L21/3065 , H01L29/165 , H01L29/66636
摘要： The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess.
摘要翻译：本公开提供了一种制造半导体器件的方法，其包括提供硅衬底，在硅衬底上形成栅极堆叠，对衬底执行偏置的干蚀刻工艺以去除硅衬底的一部分，从而形成凹陷区域在硅衬底中，对硅衬底中的凹陷区域进行非偏置蚀刻工艺，从而在硅衬底中形成瓶颈形凹部区域，并且在瓶颈形凹部区域中生长半导体材料在硅衬底中。一个实施例可以包括偏置的干蚀刻工艺，包括加入HeO2气体和HBr气体。实施例可以包括执行包括N 2气体的第一偏压干法蚀刻工艺，并执行不包括N 2气体的第二偏压干式蚀刻工艺。一个实施例可以包括通过在硅衬底中的一部分凹陷区域上添加氧气以形成氧化硅，来对硅衬底中的凹陷区域进行氧化处理。因此，这些方法形成聚合物保护以帮助形成瓶颈形凹部。

2. 发明授权

US09011599B2 Method of temperature determination for deposition reactors 有权
标题翻译：沉积反应器温度测定方法
公开(公告)号：US09011599B2
公开(公告)日：2015-04-21
申请号：US12835789
申请日：2010-07-14
申请人： Jhi-Cherng Lu , Jr-Hung Li , Chii-Horng Li , Pang-Yen Tsai , Bing-Hung Chen , Tze-Liang Lee
发明人： Jhi-Cherng Lu , Jr-Hung Li , Chii-Horng Li , Pang-Yen Tsai , Bing-Hung Chen , Tze-Liang Lee
IPC分类号： C30B25/08 , C30B25/16 , C30B29/06 , C30B29/08 , C30B29/52 , H01L21/02 , H01L21/66
CPC分类号： C30B25/16 , C30B29/06 , C30B29/08 , C30B29/52 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L22/10 , H01L22/12 , Y10T117/1004 , Y10T117/1008
摘要： A method of determining a temperature in a deposition reactor includes the steps of depositing a first epitaxial layer of silicon germanium on a substrate, depositing a second epitaxial layer of silicon above the first epitaxial layer, measuring the thickness of the second epitaxial layer and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer. The method may also include heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device and generating a signal indicative of a temperature within the deposition reactor. The method may also contain the steps of comparing the measured thickness with a predetermined thickness of the second epitaxial layer corresponding to the predetermined temperature and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and the predetermined thickness of the second epitaxial layer.
摘要翻译：确定沉积反应器中的温度的方法包括以下步骤：将硅锗的第一外延层沉积在衬底上，在第一外延层上沉积硅的第二外延层，测量第二外延层的厚度并确定使用测量的第二外延层的厚度在沉积反应器中进行温度测量。该方法还可以包括使用加热装置和温度测量装置将沉积反应器加热至约预定温度，并产生指示沉积反应器内的温度的信号。该方法还可以包括以下步骤：将测量的厚度与对应于预定温度的第二外延层的预定厚度进行比较，并使用第二外延层的测量厚度和第二外延层的预定厚度来确定沉积反应器中的温度外延层。

3. 发明授权

US08889501B2 Methods for forming MOS devices with raised source/drain regions 有权
标题翻译：用于形成具有升高的源极/漏极区域的MOS器件的方法
公开(公告)号：US08889501B2
公开(公告)日：2014-11-18
申请号：US13486240
申请日：2012-06-01
申请人： Harry-Hak-Lay Chuang , Sin-Hua Wu , Chung-Hau Fei , Ming Zhu , Bao-Ru Young , Yen-Ru Lee , Chii-Horng Li , Tze-Liang Lee
发明人： Harry-Hak-Lay Chuang , Sin-Hua Wu , Chung-Hau Fei , Ming Zhu , Bao-Ru Young , Yen-Ru Lee , Chii-Horng Li , Tze-Liang Lee
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/11
CPC分类号： H01L27/1116 , H01L21/823807 , H01L21/823814
摘要： A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor.
摘要翻译：一种方法包括在半导体衬底上形成第一器件的第一栅极堆叠，以及在半导体衬底上形成第二MOS器件的第二栅极堆叠。执行第一外延以形成用于第二MOS器件的源/漏应力源，其中源极/漏极应力器与第二栅极堆叠相邻。执行第二外延以同时形成第一硅层和第二硅层，其中第一硅层位于半导体衬底的第一部分之上并且与第一栅极堆叠相邻。第二硅层与源极/漏极应力源重叠。

4. 发明授权

US08530316B2 Method for fabricating a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08530316B2
公开(公告)日：2013-09-10
申请号：US13736453
申请日：2013-01-08
申请人： Yu-Hung Cheng , Jhi-Cherng Lu , Ming-Hua Yu , Chii-Horng Li , Tze-Liang Lee
发明人： Yu-Hung Cheng , Jhi-Cherng Lu , Ming-Hua Yu , Chii-Horng Li , Tze-Liang Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/20 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02636 , H01L21/3065 , H01L21/823412 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L29/66477 , H01L29/7848
摘要： A method for fabricating a semiconductor device, the method including growing a first semiconductor structure comprising a first semiconductor material on a surface of a substrate, wherein growing the first semiconductor structure includes forming a semiconductor particle comprising the first semiconductor material on a second semiconductor structure of the semiconductor device. The method further includes forming a protection layer of a second semiconductor material on the first semiconductor structure, wherein forming the protection layer includes forming the protection layer on the semiconductor particle. The method further includes removing a portion of the protection layer, wherein removing the portion of the protection layer includes fully removing the protection layer on the semiconductor particle and the semiconductor particle.
摘要翻译：一种制造半导体器件的方法，所述方法包括在衬底的表面上生长包括第一半导体材料的第一半导体结构，其中生长第一半导体结构包括在第二半导体结构的第二半导体结构上形成包含第一半导体材料的半导体粒子半导体器件。该方法还包括在第一半导体结构上形成第二半导体材料的保护层，其中形成保护层包括在半导体颗粒上形成保护层。该方法还包括去除保护层的一部分，其中去除保护层的部分包括完全去除半导体颗粒和半导体颗粒上的保护层。

5. 发明授权

US08450161B2 Method of fabricating a sealing structure for high-k metal gate 有权
标题翻译：制造高k金属栅极密封结构的方法
公开(公告)号：US08450161B2
公开(公告)日：2013-05-28
申请号：US13465551
申请日：2012-05-07
申请人： Chien-Hao Chen , Hao-Ming Lien , Ssu-Yu Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Liang Chen , Chung-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang
发明人： Chien-Hao Chen , Hao-Ming Lien , Ssu-Yu Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Liang Chen , Chung-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang
IPC分类号： H01L21/00 , H01L21/02
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
摘要翻译：本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域密封层的边缘。

6. 发明授权

US08294216B2 Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors 有权
标题翻译：将I / O和核心MOS器件的形成与MOS电容器和电阻器集成
公开(公告)号：US08294216B2
公开(公告)日：2012-10-23
申请号：US12191817
申请日：2008-08-14
申请人： Harry Chuang , Mong Song Liang , Wen-Chih Yang , Chien-Liang Chen , Chii-Horng Li
发明人： Harry Chuang , Mong Song Liang , Wen-Chih Yang , Chien-Liang Chen , Chii-Horng Li
IPC分类号： H01L27/11
CPC分类号： H01L27/0629 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L28/20 , H01L28/40 , H01L29/94
摘要： An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.
摘要翻译：集成电路结构包括半导体衬底和第一和第二MOS器件。第一MOS器件包括半导体衬底上的第一栅极电介质，其中第一栅极电介质是平面的; 以及位于第一栅极电介质上的第一栅电极。第二MOS器件包括半导体衬底上的第二栅极电介质; 以及在所述第二栅极电介质上方的第二栅电极。第二栅电极的高度大于第一栅电极的高度。第二栅极电介质包括在第二栅电极下面的平面部分和在第二栅电极的侧壁上延伸的侧壁部分。

7. 发明申请

US20120168821A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120168821A1
公开(公告)日：2012-07-05
申请号：US12984877
申请日：2011-01-05
申请人： Yu-Hung CHENG , Chii-Horng LI , Tze-Liang LEE
发明人： Yu-Hung CHENG , Chii-Horng LI , Tze-Liang LEE
IPC分类号： H01L29/38 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/78 , H01L29/7848
摘要： A semiconductor device having a substrate including a major surface, a gate stack comprising a sidewall over the substrate and a spacer over the substrate adjoining the sidewall of the gate stack. The spacer having a bottom surface having an outer point that is the point on the bottom surface farthest from the gate stack. An isolation structure in the substrate on one side of the gate stack has an outer edge closest to the spacer. A strained material below the major surface of the substrate disposed between the spacer and the isolation structure having an upper portion and a lower portion separated by a transition plane at an acute angle to the major surface of the substrate.
摘要翻译：一种具有包括主表面的衬底的半导体器件，包括在衬底上的侧壁的栅极堆叠以及与栅极堆叠的侧壁相邻的衬底上的间隔物。该间隔件具有底表面，该外表面是位于最远离该栅极叠层的底表面上的点。在栅极堆叠的一侧上的衬底中的隔离结构具有最靠近间隔物的外边缘。位于衬垫的主表面之下的应变材料设置在间隔件和隔离结构之间，该上表面和隔离结构具有与衬底的主表面成锐角的过渡面分开的上部和下部。

8. 发明申请

US20110287611A1 Reducing Variation by Using Combination Epitaxy Growth 有权
标题翻译：通过组合外延生长减少变异
公开(公告)号：US20110287611A1
公开(公告)日：2011-11-24
申请号：US13030850
申请日：2011-02-18
申请人： Yu-Hung Cheng , Chii-Horng Li , Tze-Liang Lee , Yi-Hung Lin
发明人： Yu-Hung Cheng , Chii-Horng Li , Tze-Liang Lee , Yi-Hung Lin
IPC分类号： H01L21/20
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/02573 , H01L21/0262 , H01L21/02636 , H01L21/02639 , H01L29/0847 , H01L29/7848
摘要： A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (E/G) ratio of process gases used in the first growth stage; and performing a second growth stage with a second E/G ratio of process gases used in the second growth stage different from the first E/G ratio.
摘要翻译：一种用于形成半导体结构的方法包括在晶片上的半导体衬底上形成栅叠层; 在所述半导体衬底中形成凹槽并邻近所述栅叠层; 以及进行选择性外延生长以在所述凹部中生长半导体材料以形成外延区域。执行选择性外延生长的步骤包括以第一生长阶段中使用的工艺气体的第一生长蚀刻（E / G）比率进行第一生长阶段; 以及在与第一E / G比不同的第二生长阶段中使用的处理气体的第二E / G比进行第二生长阶段。

9. 发明申请

US20100044803A1 SEALING STRUCTURE FOR HIGH-K METAL GATE AND METHOD OF MAKING 有权
标题翻译：高K金属门的密封结构及其制备方法
公开(公告)号：US20100044803A1
公开(公告)日：2010-02-25
申请号：US12389535
申请日：2009-02-20
申请人： Chien-Hao Chen , Hao-Ming Lien , Ssu-Yi Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Liang Chen , Chung-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang
发明人： Chien-Hao Chen , Hao-Ming Lien , Ssu-Yi Li , Jun-Lin Yeh , Kang-Cheng Lin , Kuo-Tai Huang , Chii-Horng Li , Chien-Liang Chen , Chung-Hau Fei , Wen-Chih Yang , Jin-Aun Ng , Chi Hsin Chang , Chun Ming Lin , Harry Chuang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
摘要翻译：本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域密封层的边缘。

10. 发明授权

US08927374B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08927374B2
公开(公告)日：2015-01-06
申请号：US13252346
申请日：2011-10-04
申请人： Lilly Su , Pang-Yen Tsai , Tze-Liang Lee , Chii-Horng Li , Yen-Ru Lee , Ming-Hua Yu
发明人： Lilly Su , Pang-Yen Tsai , Tze-Liang Lee , Chii-Horng Li , Yen-Ru Lee , Ming-Hua Yu
IPC分类号： H01L21/336 , H01L29/04 , H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/78 , H01L29/08
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/0617 , H01L29/045 , H01L29/0653 , H01L29/0843 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of the substrate to enhance carrier mobility and upgrade the device performance. The improved formation method is achieved by providing a treatment to redistribute at least a portion of the corner in the cavity.
摘要翻译：公开了一种制造半导体器件的方法。应变材料形成在衬底的空腔中并与衬底中的隔离结构相邻。应变材料在基底表面上方有一角。所公开的方法提供了一种用于在隔离结构附近形成应变材料的改进方法，其中在衬底的空腔中增加部分以增强载体移动性并提高器件性能。改进的形成方法通过提供一种处理来重新分布空腔中角部的至少一部分来实现。

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