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1. 发明申请

US20160226491A1 METHOD AND APPARATUS FOR FACILITATING COMMUNICATION BETWEEN PROGRAMMABLE LOGIC CIRCUIT AND APPLICATION SPECIFIC INTEGRATED CIRCUIT WITH CLOCK ADJUSTMENT 审中-公开
标题翻译：用于促进可编程逻辑电路与具有时钟调整的应用特定集成电路之间的通信的方法和装置
公开(公告)号：US20160226491A1
公开(公告)日：2016-08-04
申请号：US14612076
申请日：2015-02-02
申请人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
发明人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
IPC分类号： H03K19/0175 , H03K19/177 , H03K19/02
CPC分类号： H03K19/017581 , H03K19/02 , H03K19/17736
摘要： A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.
摘要翻译：公开了一种包含专用集成电路（“ASIC”）和现场可编程门阵列（“FPGA”）的逻辑处理装置，能够自动连接ASIC和FPGA。逻辑处理装置在一个方面包括相位调整电路，ASIC和可配置逻辑电路（“CLC”），其中CLC可以是FPGA。虽然ASIC能够根据ASIC时钟域执行特定功能，但是CLC能够根据FPGA时钟域执行可编程逻辑功能。相位调整电路用于根据ASIC时钟域和FPGA时钟域来自动促进ASIC和CLC之间的通信。

2. 发明申请

US20110080907A1 Method and Apparatus for Specifying IP Termination in a Network Element 审中-公开
标题翻译：用于指定网络元素中的IP终端的方法和装置
公开(公告)号：US20110080907A1
公开(公告)日：2011-04-07
申请号：US12966733
申请日：2010-12-13
申请人： Ameel Kamboh , David Tsang
发明人： Ameel Kamboh , David Tsang
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , H04L12/4641 , H04L45/308 , H04L45/54 , H04L47/20
摘要： IP applications may be hosted on processors other than the processor on which their associated routing entity is hosted by causing the routing context to be extended to the new processor and causing IP termination to occur at the new processor. Applications may define policies specifying packet attributes and actions to be taken on matching packets, so that packets matching the policy may be directed to a processor hosting the application rather than a processor hosting the routing entity. A steering policy manager may be implemented to receive policies from the applications, verify the policy format and uniqueness vis-à-vis previously implemented policies, and implement the policies by passing the policies to one or more steering policy agents. Filters may be programmed into the data plane or the control plane to cause IP termination to occur on the processor hosting the application.
摘要翻译： IP应用可以通过使路由上下文被扩展到新的处理器并导致在新的处理器上发生IP终止而被托管在除了其相关联的路由实体所在的处理器之外的处理器上。应用可以定义指定要在匹配分组上执行的分组属性和动作的策略，使得与策略匹配的分组可以被引导到承载应用的处理器，而不是托管路由实体的处理器。可以实施转向政策经理以从应用程序接收策略，验证策略格式和对先前实施的策略的唯一性，并通过将策略传递给一个或多个指导策略代理来实施策略。滤波器可以被编程到数据平面或控制平面中，以在承载应用的处理器上发生IP终止。

3. 发明授权

US07869442B1 Method and apparatus for specifying IP termination in a network element 有权
标题翻译：用于指定网络元件中的IP终端的方法和装置
公开(公告)号：US07869442B1
公开(公告)日：2011-01-11
申请号：US11241612
申请日：2005-09-30
申请人： Ameel Kamboh , David Tsang
发明人： Ameel Kamboh , David Tsang
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , H04L12/4641 , H04L45/308 , H04L45/54 , H04L47/20
摘要： IP applications may be hosted on processors other than the processor on which their associated routing entity is hosted by causing the routing context to be extended to the new processor and causing IP termination to occur at the new processor. Applications may define policies specifying packet attributes and actions to be taken on matching packets, so that packets matching the policy may be directed to a processor hosting the application rather than a processor hosting the routing entity. A steering policy manager may be implemented to receive policies from the applications, verify the policy format and uniqueness vis-à-vis previously implemented policies, and implement the policies by passing the policies to one or more steering policy agents. Filters may be programmed into the data plane or the control plane to cause IP termination to occur on the processor hosting the application.
摘要翻译： IP应用可以通过使路由上下文被扩展到新的处理器并导致在新的处理器上发生IP终止而被托管在除了其相关联的路由实体所在的处理器之外的处理器上。应用可以定义指定要在匹配分组上执行的分组属性和动作的策略，使得与策略匹配的分组可以被引导到承载应用的处理器，而不是托管路由实体的处理器。可以实施转向政策经理以从应用程序接收策略，验证策略格式和对先前实施的策略的唯一性，并通过将策略传递给一个或多个指导策略代理来实施策略。滤波器可以被编程到数据平面或控制平面中，以在承载应用的处理器上发生IP终止。

4. 发明授权

US06977838B1 Method and system for providing a programmable current source for a magnetic memory 有权
标题翻译：为磁存储器提供可编程电流源的方法和系统
公开(公告)号：US06977838B1
公开(公告)日：2005-12-20
申请号：US10781482
申请日：2004-02-17
申请人： David Tsang , Xizeng Shi , Po-Kang Wang , Hsu Kai (Karl) Yang , David Hu
发明人： David Tsang , Xizeng Shi , Po-Kang Wang , Hsu Kai (Karl) Yang , David Hu
IPC分类号： G11C20060101 , G11C5/14 , G11C11/00 , G11C11/16 , G11C13/00
CPC分类号： G11C11/16 , G11C5/145
摘要： A method and system for providing a magnetic memory are disclosed. The method and system include providing a plurality of magnetic memory cells and at least one programmable current source. Each of the plurality of magnetic memory cells includes a first magnetic element. The programmable current source(s) are for programming a portion of the plurality of magnetic memory cells. Each of the programmable current source(s) includes a controller and a current source coupled to the controller. The controller is for determining a current provided by the current source and includes at least a second magnetic element. The second magnetic element(s) are substantially the same as the first magnetic element. The controller determines the current provided by the current source based on the at least the second magnetic element.
摘要翻译：公开了一种用于提供磁存储器的方法和系统。该方法和系统包括提供多个磁存储器单元和至少一个可编程电流源。多个磁存储单元中的每一个包括第一磁性元件。可编程电流源用于对多个磁存储单元的一部分进行编程。每个可编程电流源包括耦合到控制器的控制器和电流源。控制器用于确定由电流源提供的电流并且包括至少第二磁性元件。第二磁性元件基本上与第一磁性元件相同。控制器基于至少第二磁性元件确定由电流源提供的电流。

5. 发明授权

US06864551B2 High density and high programming efficiency MRAM design 失效
标题翻译：高密度和高编程效率的MRAM设计
公开(公告)号：US06864551B2
公开(公告)日：2005-03-08
申请号：US10606612
申请日：2003-06-26
申请人： David Tsang
发明人： David Tsang
IPC分类号： G11C20060101 , H01L21/8246 , H01L27/22 , H01L29/82 , H01L31/062 , H01L43/00
CPC分类号： H01L27/228 , B82Y10/00
摘要： A method and system for providing a magnetic memory is disclosed. The magnetic memory includes a magnetic element. The magnetic element is written using a first write line and a second write line and resides at an intersection between the first and second write lines. The second write line is oriented at an angle to the first write line. The second write line has a top and at least one side. At least a portion of the second write line is covered by an insulating layer. A magnetic layer covers a portion of the insulating layer. The portion of the insulating layer resides between the magnetic layer and the second write line. The magnetic layer includes a soft magnetic material.
摘要翻译：公开了一种用于提供磁存储器的方法和系统。磁存储器包括磁性元件。使用第一写入线和第二写入线写入磁性元件，并且驻留在第一和第二写入线之间的交叉点处。第二写入线与第一写入线成一定角度。第二个写入行具有顶部和至少一个侧面。第二写入线的至少一部分被绝缘层覆盖。磁性层覆盖绝缘层的一部分。绝缘层的部分位于磁性层和第二写入线之间。磁性层包括软磁性材料。

6. 发明授权

US06982916B2 Method and system for providing temperature dependent programming for magnetic memories 失效
标题翻译：用于为磁存储器提供温度依赖编程的方法和系统
公开(公告)号：US06982916B2
公开(公告)日：2006-01-03
申请号：US10778781
申请日：2004-02-12
申请人： David Tsang
发明人： David Tsang
IPC分类号： G11C7/04
CPC分类号： G11C11/16
摘要： A method and system for programming a magnetic memory including a plurality of magnetic elements is disclosed. The method and system include sensing a temperature of the magnetic memory and providing an indication of the temperature of the magnetic memory. The method and system also include providing a current that is based on the indication of temperature of the magnetic memory. The current is temperature dependent and can be used in programming at least a portion of the magnetic elements without the addition of a separately generated current. In addition, the method and system include carrying for at least a portion of the plurality of magnetic elements. The temperature is preferably sensed by at least one temperature sensor, while the current is preferably provided by a current source coupled with the temperature sensor(s).
摘要翻译：公开了一种用于对包括多个磁性元件的磁存储器进行编程的方法和系统。该方法和系统包括感测磁存储器的温度并提供磁存储器的温度的指示。该方法和系统还包括提供基于磁存储器的温度指示的电流。电流是温度依赖性的，并且可以用于编程至少一部分磁性元件而不增加单独产生的电流。此外，该方法和系统包括承载多个磁性元件的至少一部分。温度优选地由至少一个温度传感器感测，而电流优选地由与温度传感器耦合的电流源提供。

7. 发明授权

US06963500B2 Magnetic tunneling junction cell array with shared reference layer for MRAM applications 失效
标题翻译：具有用于MRAM应用的共享参考层的磁隧道结电池阵列
公开(公告)号：US06963500B2
公开(公告)日：2005-11-08
申请号：US10781131
申请日：2004-02-17
申请人： David Tsang
发明人： David Tsang
IPC分类号： G11C11/15 , G11C11/14
CPC分类号： G11C11/15
摘要： A method and system for providing a magnetic memory is disclosed. The method and system include providing a plurality of magnetic elements and a plurality of reference layers. Each of the magnetic elements includes a free layer and a spacer layer. Each of the reference layers is coupled with a corresponding portion of the magnetic elements. The reference layers are ferromagnetic. A portion of each reference layer functions as at least a portion of a pinned layer for each of the corresponding portion of the magnetic elements. The portion of each of the plurality of reference layers also functions as a write line for the corresponding portion of the plurality of magnetic elements. The spacer layer resides between the free layer of each of the plurality of magnetic elements and the reference layer.
摘要翻译：公开了一种用于提供磁存储器的方法和系统。该方法和系统包括提供多个磁性元件和多个参考层。每个磁性元件包括自由层和间隔层。每个参考层与磁性元件的对应部分耦合。参考层是铁磁性的。每个参考层的一部分用作磁性元件的相应部分中的每一个的被钉扎层的至少一部分。多个参考层中的每一个的部分也用作多个磁性元件的对应部分的写入线。间隔层位于多个磁性元件中的每一个的自由层和参考层之间。

8. 发明授权

US06933550B2 Method and system for providing a magnetic memory having a wrapped write line 失效
标题翻译：用于提供具有包裹的写入线的磁存储器的方法和系统
公开(公告)号：US06933550B2
公开(公告)日：2005-08-23
申请号：US10781478
申请日：2004-02-17
申请人： David Tsang
发明人： David Tsang
IPC分类号： G11C11/15 , H01L31/119 , G11C7/02
CPC分类号： G11C11/15
摘要： A method and system for providing magnetic memory are disclosed. The method and system include providing a plurality of magnetic memory elements and providing at least one wrapped write line. Each wrapped write line includes a bottom write line and a top write line electrically connected to the bottom write line. The bottom write line resides below a portion of the plurality of magnetic elements, while the top write resides above the portion of the plurality of magnetic elements. The bottom write line carries a first current in a first direction, while the top write line carries a second current in a second direction opposite to the first direction.
摘要翻译：公开了一种用于提供磁存储器的方法和系统。该方法和系统包括提供多个磁存储器元件并且提供至少一个封装的写入线。每个封装的写行包括底部写入线和电连接到底部写入线的顶部写入线。底部写入线位于多个磁性元件的一部分下方，而顶部写入位于多个磁性元件的部分之上。底部写入线在第一方向上承载第一电流，而顶部写入线在与第一方向相反的第二方向上承载第二电流。

9. 发明授权

US06812538B2 MRAM cells having magnetic write lines with a stable magnetic state at the end regions 失效
标题翻译：具有在端部区域具有稳定磁状态的磁写入线的MRAM单元
公开(公告)号：US06812538B2
公开(公告)日：2004-11-02
申请号：US10669216
申请日：2003-09-23
申请人： David Tsang
发明人： David Tsang
IPC分类号： H01L2982
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/15
摘要： A method and system for providing and using a magnetic memory are disclosed. The magnetic memory includes a plurality of magnetic memory cells, a plurality of magnetic write lines and a plurality of magnetic biasing structures. The plurality of magnetic write lines have a plurality of end regions. The plurality of magnetic biasing structures coupled to the plurality of end regions of the plurality of magnetic write lines.
摘要翻译：公开了一种用于提供和使用磁存储器的方法和系统。磁存储器包括多个磁存储单元，多个磁写线和多个磁偏置结构。多个磁写入线具有多个端部区域。多个磁偏置结构耦合到多个磁写入线的多个端部区域。

10. 发明申请

US20180062654A9 METHOD AND APPARATUS FOR FACILITATING COMMUNICATION BETWEEN PROGRAMMABLE LOGIC CIRCUIT AND APPLICATION SPECIFIC INTEGRATED CIRCUIT WITH CLOCK ADJUSTMENT 审中-公开
公开(公告)号：US20180062654A9
公开(公告)日：2018-03-01
申请号：US14612076
申请日：2015-02-02
申请人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
发明人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
IPC分类号： H03K19/0175 , H03K19/02 , H03K19/177
CPC分类号： H03K19/017581 , H03K19/02 , H03K19/17736
摘要： A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

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