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1. 发明申请

US20160226491A1 METHOD AND APPARATUS FOR FACILITATING COMMUNICATION BETWEEN PROGRAMMABLE LOGIC CIRCUIT AND APPLICATION SPECIFIC INTEGRATED CIRCUIT WITH CLOCK ADJUSTMENT 审中-公开
标题翻译：用于促进可编程逻辑电路与具有时钟调整的应用特定集成电路之间的通信的方法和装置
公开(公告)号：US20160226491A1
公开(公告)日：2016-08-04
申请号：US14612076
申请日：2015-02-02
申请人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
发明人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
IPC分类号： H03K19/0175 , H03K19/177 , H03K19/02
CPC分类号： H03K19/017581 , H03K19/02 , H03K19/17736
摘要： A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.
摘要翻译：公开了一种包含专用集成电路（“ASIC”）和现场可编程门阵列（“FPGA”）的逻辑处理装置，能够自动连接ASIC和FPGA。逻辑处理装置在一个方面包括相位调整电路，ASIC和可配置逻辑电路（“CLC”），其中CLC可以是FPGA。虽然ASIC能够根据ASIC时钟域执行特定功能，但是CLC能够根据FPGA时钟域执行可编程逻辑功能。相位调整电路用于根据ASIC时钟域和FPGA时钟域来自动促进ASIC和CLC之间的通信。

2. 发明申请

US20180062654A9 METHOD AND APPARATUS FOR FACILITATING COMMUNICATION BETWEEN PROGRAMMABLE LOGIC CIRCUIT AND APPLICATION SPECIFIC INTEGRATED CIRCUIT WITH CLOCK ADJUSTMENT 审中-公开
公开(公告)号：US20180062654A9
公开(公告)日：2018-03-01
申请号：US14612076
申请日：2015-02-02
申请人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
发明人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
IPC分类号： H03K19/0175 , H03K19/02 , H03K19/177
CPC分类号： H03K19/017581 , H03K19/02 , H03K19/17736
摘要： A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

3. 发明授权

US09043688B1 Error data generation and application for disk drive applications 有权
标题翻译：磁盘驱动器应用程序的错误数据生成和应用程序
公开(公告)号：US09043688B1
公开(公告)日：2015-05-26
申请号：US13427599
申请日：2012-03-22
申请人： Kai Keung Chan , Xin-Ning Song , Jason Bellorado , Kwok W. Yeung
发明人： Kai Keung Chan , Xin-Ning Song , Jason Bellorado , Kwok W. Yeung
IPC分类号： H03M13/03 , H03M13/41 , H04L1/00 , G11B20/10 , H03M13/29
CPC分类号： H03M13/41 , G11B20/10009 , G11B20/10268 , H03M13/1111 , H03M13/2957 , H03M13/3723 , H03M13/4107 , H03M13/4146 , H03M13/6325 , H03M13/6343 , H04L1/0054 , H04L1/0059
摘要： Generating error data associated with decoding data is disclosed, including: processing an input sequence of samples associated with data stored on media using a detector and a decoder during a global iteration; and generating one or more error values based at least in part on one or more decision bits output by the detector or the decoder and the input sequence of samples.
摘要翻译：公开了生成与解码数据相关联的错误数据，包括：在全局迭代期间使用检测器和解码器处理与存储在媒体上的数据相关联的样本的输入序列; 以及至少部分地基于由所述检测器或所述解码器输出的一个或多个判定位和所述输入样本序列来生成一个或多个误差值。

4. 发明申请

US20120019950A1 PAD BIT INJECTION DURING READ OPERATION TO IMPROVE FORMAT EFFICIENCY 有权
标题翻译：读取操作期间的PAD位注入以提高格式效率
公开(公告)号：US20120019950A1
公开(公告)日：2012-01-26
申请号：US13113926
申请日：2011-05-23
申请人： Kwok W. Yeung , Kai Keung Chan , Paul K. Lai
发明人： Kwok W. Yeung , Kai Keung Chan , Paul K. Lai
IPC分类号： G11B5/09
CPC分类号： G11B5/09
摘要： Injecting pad bits during a read operation to improve format efficiency is disclosed. In some embodiments, a pad sequence associated with error correction is not stored in a sector on a disk. Instead, the pad sequence is merged at a read channel with data stored in a sector that is accessed by the read channel.
摘要翻译：公开了在读取操作期间注入焊盘位以提高格式效率。在一些实施例中，与纠错相关联的填充序列不存储在盘上的扇区中。相反，焊盘序列在读通道上与存储在由读通道访问的扇区中的数据合并。

5. 发明授权

US08077814B2 Preamble acquisition without second order timing loops 有权
标题翻译：前导采集无二阶定时循环
公开(公告)号：US08077814B2
公开(公告)日：2011-12-13
申请号：US12960043
申请日：2010-12-03
申请人： Haitao Xia , Shih-Ming Shih , Ryan Yu , Marcus Marrow , Kai Keung Chan
发明人： Haitao Xia , Shih-Ming Shih , Ryan Yu , Marcus Marrow , Kai Keung Chan
IPC分类号： H04L27/06
CPC分类号： H04L7/08
摘要： A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop.
摘要翻译：通过获得与数据分组的前导部分相关联的第一多个样本和第二多个样本来调整时钟。使用时钟对第一多个采样和第二多个采样进行采样。至少部分地基于第一多个样本确定第一中间值，并且至少部分地基于第二多个样本来确定第二中间值。至少部分地基于第一中间值和第二中间值来确定与前导码部分的结尾相关联的结束值。时钟至少部分地基于结束值进行调整，而不使用二阶定时循环。

6. 发明授权

US07974033B1 Pad bit injection during read operation to improve format efficiency 有权
标题翻译：读取操作期间的Pad位注入以提高格式效率
公开(公告)号：US07974033B1
公开(公告)日：2011-07-05
申请号：US11787230
申请日：2007-04-13
申请人： Kwok W. Yeung , Kai Keung Chan , Paul K. Lai
发明人： Kwok W. Yeung , Kai Keung Chan , Paul K. Lai
IPC分类号： G11B5/09 , G11B5/02
CPC分类号： G11B5/09
摘要： Injecting pad bits during a read operation to improve format efficiency is disclosed. In some embodiments, a pad sequence associated with error correction is not stored in a sector on a disk. Instead, the pad sequence is merged at a read channel with data stored in a sector that is accessed by the read channel.
摘要翻译：公开了在读取操作期间注入焊盘位以提高格式效率。在一些实施例中，与纠错相关联的填充序列不存储在盘上的扇区中。相反，焊盘序列在读通道上与存储在由读通道访问的扇区中的数据合并。

7. 发明申请

US20110075779A1 PREAMBLE ACQUISITION WITHOUT SECOND ORDER TIMING LOOPS 有权
标题翻译：前瞻性收购，没有第二个订单时机
公开(公告)号：US20110075779A1
公开(公告)日：2011-03-31
申请号：US12960043
申请日：2010-12-03
申请人： Haitao Xia , Shih-Ming Shih , Ryan Yu , Marcus Marrow , Kai Keung Chan
发明人： Haitao Xia , Shih-Ming Shih , Ryan Yu , Marcus Marrow , Kai Keung Chan
IPC分类号： H04L7/00
CPC分类号： H04L7/08
摘要： A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop.
摘要翻译：通过获得与数据分组的前导部分相关联的第一多个样本和第二多个样本来调整时钟。使用时钟对第一多个采样和第二多个采样进行采样。至少部分地基于第一多个样本确定第一中间值，并且至少部分地基于第二多个样本来确定第二中间值。至少部分地基于第一中间值和第二中间值来确定与前导码部分的结尾相关联的结束值。时钟至少部分地基于结束值进行调整，而不使用二阶定时循环。

8. 发明授权

US06677793B1 Automatic delay matching circuit for data serializer 有权
标题翻译：数据串行器的自动延迟匹配电路
公开(公告)号：US06677793B1
公开(公告)日：2004-01-13
申请号：US10357827
申请日：2003-02-03
申请人： Kai Keung Chan , Jung-Sheng Hoei , Pankaj Joshi , Leo Fang
发明人： Kai Keung Chan , Jung-Sheng Hoei , Pankaj Joshi , Leo Fang
IPC分类号： H03L706
CPC分类号： H03L7/23 , H03L7/0805 , H03L7/0812
摘要： An automatic delay matching circuit for a data serializer includes a phase-locked loop for synthesizing a transmitter clock signal for an external circuit, a phase interpolator coupled to the phase-locked loop for delaying or advancing the transmitter clock signal in response to a phase control signal to generate a delayed or advanced transmitter clock signal for the data serializer, a phase detector for measuring a phase difference between the delayed or advanced transmitter clock signal further delayed through the data serializer and the transmitter clock signal delayed through an external circuit, and a loop filter coupled to the phase detector for generating the phase control signal as a function of the phase difference between the delayed or advanced transmitter clock signal further delayed through the data serializer and the transmitter clock signal delayed through the external circuit.
摘要翻译：用于数据串行器的自动延迟匹配电路包括用于合成用于外部电路的发射机时钟信号的锁相环，耦合到锁相环的相位插值器，用于响应于相位控制延迟或前进发送器时钟信号产生用于数据串行器的延迟或高级发送器时钟信号的相位检测器，用于测量通过数据串行器进一步延迟的延迟或高级发送器时钟信号与通过外部电路延迟的发送器时钟信号之间的相位差的相位检测器，以及耦合到相位检测器，用于根据通过数据串行器进一步延迟的延迟或高级发送器时钟信号与通过外部电路延迟的发送器时钟信号之间的相位差产生相位控制信号。

9. 发明授权

US08631311B1 Data recovery using existing reconfigurable read channel hardware 有权
标题翻译：使用现有的可重新配置的读通道硬件进行数据恢复
公开(公告)号：US08631311B1
公开(公告)日：2014-01-14
申请号：US13453729
申请日：2012-04-23
申请人： Kai Keung Chan , Yu Kou , Xin-Ning Song , Wing Hui
发明人： Kai Keung Chan , Yu Kou , Xin-Ning Song , Wing Hui
IPC分类号： G06F11/00
CPC分类号： H04L1/0045 , H04L1/0057
摘要： A method for recovering data is disclosed. A sensed analog signal is converted into digital samples using an analog-to-digital converter (ADC). The digital samples are processed into processed digital samples using a first filter. The processed digital samples are decoded into decoded data. Whether the decoded data is acceptable is then determined. The processed digital samples are fed back to the first filter using a reprocessing circuit such that the processed digital samples are reprocessed into reprocessed digital samples in the event that the decoded data is unacceptable. A set of reprocessing coefficients is provided for the first filter to reprocess the processed digital samples.
摘要翻译：公开了一种恢复数据的方法。感测的模拟信号使用模数转换器（ADC）转换成数字采样。使用第一滤波器将数字样本处理成经处理的数字样本。经处理的数字样本被解码成解码数据。然后确定解码数据是否可接受。使用再处理电路将经处理的数字样本反馈到第一滤波器，使得在解码数据不可接受的情况下，经处理的数字样本被重新处理成再处理的数字样本。提供一组再处理系数用于第一滤波器以重新处理经处理的数字样本。

10. 发明申请

US20130027801A1 INTER-TRACK INTERFERENCE CANCELATION IN THE PRESENCE OF FREQUENCY OFFSET 有权
标题翻译：频率偏移存在的互扰干扰消除
公开(公告)号：US20130027801A1
公开(公告)日：2013-01-31
申请号：US13448218
申请日：2012-04-16
申请人： Naveen Kumar , Jason Bellorado , Marcus Marrow , Kai Keung Chan
发明人： Naveen Kumar , Jason Bellorado , Marcus Marrow , Kai Keung Chan
IPC分类号： G11B20/10
CPC分类号： G11B5/012 , G11B19/045 , G11B20/10046 , G11B2005/0002 , G11B2020/1238 , G11B2020/1292 , G11B2020/1298 , G11B2220/2516
摘要： An initial phase offset between a center track and a side track is determined. An initial side track pulse shape is determined using the initial phase offset and side track interference. The initial side track pulse shape minimizes a contribution of the side track interference to a center track bit. The contribution of the side track interference is removed from the center track bit using the initial side track pulse shape and the side track interference.
摘要翻译：确定中心轨道和侧轨迹之间的初始相位偏移。使用初始相位偏移和侧轨道干扰来确定初始侧轨道脉冲形状。初始侧轨道脉冲形状使得侧轨道干涉对中心轨道位的贡献最小化。使用初始侧轨道脉冲形状和侧轨道干扰，从中心轨道位置去除侧轨道干涉的贡献。

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