专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06353552B2 PLD with on-chip memory having a shadow register 有权
标题翻译：具有片上存储器的PLD具有影子寄存器
公开(公告)号：US06353552B2
公开(公告)日：2002-03-05
申请号：US09817951
申请日：2001-03-26
申请人： Stephen P. Sample , Michael R. Butts , Kevin A. Norman , Rakesh H. Patel , Chao Chiang Chen
发明人： Stephen P. Sample , Michael R. Butts , Kevin A. Norman , Rakesh H. Patel , Chao Chiang Chen
IPC分类号： G11C700
CPC分类号： H03K19/17772 , G11C7/1006 , G11C7/1075 , G11C7/22 , G11C8/16 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/17764 , H03K19/1778
摘要： Methods and apparatus for initializing and determining the contents of a memory block in a programmable logic device. One apparatus includes a logic element, programmably configurable to implement user-defined combinatorial or registered logic functions, and a memory block to store data. The memory block is coupled to the logic element. The memory block includes a memory storage cell to store a first data bit, a shadow cell to store a second data bit, and a transfer circuit. When a first control line of a transfer circuit is asserted, the second bit is transferred from the shadow cell to the memory storage cell. When a second control line of the transfer circuit is asserted, the first bit is transferred from the memory storage cell to the shadow cell.
摘要翻译：用于初始化和确定可编程逻辑器件中的存储器块的内容的方法和装置。一种装置包括可编程地配置为实现用户定义的组合或注册的逻辑功能的逻辑元件以及用于存储数据的存储器块。存储器块耦合到逻辑元件。存储块包括存储第一数据位的存储器存储单元，用于存储第二数据位的阴影单元和传输电路。当传送电路的第一控制线被断言时，第二位从影子单元传送到存储器存储单元。当传输电路的第二控制线被断言时，第一位从存储器存储单元传送到阴影单元。

2. 发明申请

US20180062654A9 METHOD AND APPARATUS FOR FACILITATING COMMUNICATION BETWEEN PROGRAMMABLE LOGIC CIRCUIT AND APPLICATION SPECIFIC INTEGRATED CIRCUIT WITH CLOCK ADJUSTMENT 审中-公开
公开(公告)号：US20180062654A9
公开(公告)日：2018-03-01
申请号：US14612076
申请日：2015-02-02
申请人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
发明人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
IPC分类号： H03K19/0175 , H03K19/02 , H03K19/177
CPC分类号： H03K19/017581 , H03K19/02 , H03K19/17736
摘要： A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

3. 发明授权

US6011744A Programmable logic device with multi-port memory 失效
公开(公告)号：US6011744A
公开(公告)日：2000-01-04
申请号：US895516
申请日：1997-07-16
申请人： Stephen P. Sample , Michael R. Butts , Kevin A. Norman , Rakesh H. Patel , Chao Chiang Chen
发明人： Stephen P. Sample , Michael R. Butts , Kevin A. Norman , Rakesh H. Patel , Chao Chiang Chen
IPC分类号： G11C7/10 , G11C7/22 , G11C8/16 , H03K19/177 , G11C8/00
CPC分类号： H03K19/17772 , G11C7/1006 , G11C7/1075 , G11C7/22 , G11C8/16 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/17764 , H03K19/1778 , H03K19/177
摘要： An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.

4. 发明授权

US6011730A Programmable logic device with multi-port memory 有权
公开(公告)号：US6011730A
公开(公告)日：2000-01-04
申请号：US298890
申请日：1999-04-23
申请人： Stephen P. Sample , Michael R. Butts , Kevin A. Norman , Rakesh H. Patel , Chao Chiang Chen
发明人： Stephen P. Sample , Michael R. Butts , Kevin A. Norman , Rakesh H. Patel , Chao Chiang Chen
IPC分类号： G11C7/10 , G11C7/22 , G11C8/16 , H03K19/177 , G11C7/00
CPC分类号： H03K19/17772 , G11C7/1006 , G11C7/1075 , G11C7/22 , G11C8/16 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/17764 , H03K19/1778 , H03K19/177
摘要： An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.

5. 发明申请

US20070234266A1 Method of optimizing IC logic performance by static timing based parasitic budgeting 审中-公开
标题翻译：基于静态时序的寄生预算优化IC逻辑性能的方法
公开(公告)号：US20070234266A1
公开(公告)日：2007-10-04
申请号：US10774853
申请日：2004-02-07
申请人： Chao-Chiang Chen , J. Janac
发明人： Chao-Chiang Chen , J. Janac
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/78 , G06F2217/84
摘要： Increasing need to gain higher performance and lower power in semiconductor chips and field programable gate arrays requires that optimization be done in a constructive manner with respect to physical layout. Increasing perfomance by parasitic budgeting which dictates what parasitics are acceptable to meet timing and power goals is presented. Providing these controls allows the physical implementation system to skew connection parasitics in a way that makes critical components and their connections significantly faster then those in the rest of the circuit. This represent a unique advantage of existing methods and provide a unique methods to reach higher levels of performance and lower power then existing approaches.
摘要翻译：越来越需要在半导体芯片和现场可编程门阵列中获得更高的性能和更低的功耗，需要以相对于物理布局的建设性方式进行优化。提出了通过寄生预算来提高性能，从而决定了什么寄生效应可以满足时序和权力目标。提供这些控制允许物理实现系统以连接寄生效应的方式使关键组件及其连接显着快于电路其余部分。这代表了现有方法的独特优势，并提供了一种独特的方法来达到更高水平的性能，并降低现有方法的功耗。

6. 发明授权

US06219284B1 Programmable logic device with multi-port memory 有权
标题翻译：具有多端口存储器的可编程逻辑器件
公开(公告)号：US06219284B1
公开(公告)日：2001-04-17
申请号：US09405376
申请日：1999-09-24
申请人： Stephen P. Sample , Michael R. Butts , Kevin A. Norman , Rakesh H. Patel , Chao Chiang Chen
发明人： Stephen P. Sample , Michael R. Butts , Kevin A. Norman , Rakesh H. Patel , Chao Chiang Chen
IPC分类号： G11C700
CPC分类号： H03K19/17772 , G11C7/1006 , G11C7/1075 , G11C7/22 , G11C8/16 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/17764 , H03K19/1778
摘要： An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (“FPGA”), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.
摘要翻译：如本文所述的用于实现可重配置逻辑的集成电路，例如现场可编程门阵列（“FPGA”），具有多个多端口存储器块。存储器具有多个读取端口和多个写入端口。多端口存储器的每个端口可以配置为与其他端口的宽度和深度独立且独立的宽度和深度。该存储器还包括用于对存储器的内容进行同步快照或将存储器加载到初始状态的端口。存储器共享由低级逻辑元件使用的路由线，从而减轻了为了满足存储器需求而向互连网络添加路由线路的需要。

7. 发明授权

US5455525A Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array 失效
标题翻译：分层结构的可编程逻辑阵列和用于互连逻辑阵列中的逻辑元件的系统
公开(公告)号：US5455525A
公开(公告)日：1995-10-03
申请号：US162678
申请日：1993-12-06
申请人： Walford W. Ho , Chao-Chiang Chen , Yuk Y. Yang
发明人： Walford W. Ho , Chao-Chiang Chen , Yuk Y. Yang
IPC分类号： H03K19/177
CPC分类号： H03K19/17792 , H03K19/17704
摘要： A structured logic array is divided into hierarchical levels. At a highest level (the chip level), blocks are interconnected by a system of chip busses. A block interface couples each block to the chip bus system to allow the blocks to communicate with each other. At a lower level, each block includes sectors, each sector being coupled to a block bus system by a sector interface. The block bus system interconnects the sectors in each block to allow the sectors to communicate with each other. The block bus system is also coupled to the block interface to allow signals to be transferred between the block bus system and the chip bus system. At a lowest level, each sector includes a plurality of logic elements. The logic elements are interconnected by a sector bus system. The sector bus system is coupled to the sector interface to allow for the transfer of signals between the sector bus system and the block bus system.
摘要翻译：结构化逻辑阵列分为层次级别。在最高级别（芯片级），块通过芯片总线系统互连。块接口将每个块耦合到芯片总线系统以允许块彼此通信。在较低级别，每个块包括扇区，每个扇区通过扇区接口耦合到块总线系统。块总线系统将每个块中的扇区互连，以允许扇区彼此通信。块总线系统还耦合到块接口，以允许在块总线系统和芯片总线系统之间传输信号。在最低级别，每个扇区包括多个逻辑元件。逻辑元件由扇区总线系统相互连接。扇区总线系统耦合到扇区接口，以允许扇区总线系统和块总线系统之间的信号传输。

8. 发明申请

US20160226491A1 METHOD AND APPARATUS FOR FACILITATING COMMUNICATION BETWEEN PROGRAMMABLE LOGIC CIRCUIT AND APPLICATION SPECIFIC INTEGRATED CIRCUIT WITH CLOCK ADJUSTMENT 审中-公开
标题翻译：用于促进可编程逻辑电路与具有时钟调整的应用特定集成电路之间的通信的方法和装置
公开(公告)号：US20160226491A1
公开(公告)日：2016-08-04
申请号：US14612076
申请日：2015-02-02
申请人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
发明人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
IPC分类号： H03K19/0175 , H03K19/177 , H03K19/02
CPC分类号： H03K19/017581 , H03K19/02 , H03K19/17736
摘要： A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.
摘要翻译：公开了一种包含专用集成电路（“ASIC”）和现场可编程门阵列（“FPGA”）的逻辑处理装置，能够自动连接ASIC和FPGA。逻辑处理装置在一个方面包括相位调整电路，ASIC和可配置逻辑电路（“CLC”），其中CLC可以是FPGA。虽然ASIC能够根据ASIC时钟域执行特定功能，但是CLC能够根据FPGA时钟域执行可编程逻辑功能。相位调整电路用于根据ASIC时钟域和FPGA时钟域来自动促进ASIC和CLC之间的通信。

9. 发明授权

US6151258A Programmable logic device with multi-port memory 有权
标题翻译：具有多端口存储器的可编程逻辑器件
公开(公告)号：US6151258A
公开(公告)日：2000-11-21
申请号：US428019
申请日：1999-10-27
申请人： Stephen P. Sample , Michael R. Butts , Kevin A. Norman , Rakesh H. Patel , Chao Chiang Chen
发明人： Stephen P. Sample , Michael R. Butts , Kevin A. Norman , Rakesh H. Patel , Chao Chiang Chen
IPC分类号： G11C7/10 , G11C7/22 , G11C8/16 , H03K19/177 , G11C7/00
CPC分类号： H03K19/17772 , G11C7/1006 , G11C7/1075 , G11C7/22 , G11C8/16 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/17764 , H03K19/1778 , H03K19/177
摘要： An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.
摘要翻译：如本文所述的用于实现可重配置逻辑的集成电路，例如现场可编程门阵列（“FPGA”），具有多个多端口存储器块。存储器具有多个读取端口和多个写入端口。多端口存储器的每个端口可以配置为与其他端口的宽度和深度独立且独立的宽度和深度。该存储器还包括用于对存储器的内容进行同步快照或将存储器加载到初始状态的端口。存储器共享由低级逻辑元件使用的路由线，从而减轻了为了满足存储器需求而向互连网络添加路由线路的需要。

10. 发明授权

US06317367B1 FPGA with on-chip multiport memory 有权
标题翻译： FPGA具有片内多端口存储器
公开(公告)号：US06317367B1
公开(公告)日：2001-11-13
申请号：US09748088
申请日：2000-12-21
申请人： Stephen P. Sample , Michael R. Butts , Kevin A. Norman , Rakesh H. Patel , Chao Chiang Chen
发明人： Stephen P. Sample , Michael R. Butts , Kevin A. Norman , Rakesh H. Patel , Chao Chiang Chen
IPC分类号： G11C700
CPC分类号： H03K19/17772 , G11C7/1006 , G11C7/1075 , G11C7/22 , G11C8/16 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/17764 , H03K19/1778
摘要： An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (“FPGA”), as described herein has multiple blocks of multiported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multiported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.
摘要翻译：如本文所述的用于实现可重配置逻辑的集成电路，例如现场可编程门阵列（“FPGA”）具有多个多端口存储器块。存储器具有多个读取端口和多个写入端口。多端口存储器的每个端口可以配置为与其他端口的宽度和深度独立且独立的宽度和深度。该存储器还包括用于对存储器的内容进行同步快照或将存储器加载到初始状态的端口。存储器共享由低级逻辑元件使用的路由线，从而减轻了为了满足存储器需求而向互连网络添加路由线路的需要。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式