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1. 发明申请

US20160226491A1 METHOD AND APPARATUS FOR FACILITATING COMMUNICATION BETWEEN PROGRAMMABLE LOGIC CIRCUIT AND APPLICATION SPECIFIC INTEGRATED CIRCUIT WITH CLOCK ADJUSTMENT 审中-公开
标题翻译：用于促进可编程逻辑电路与具有时钟调整的应用特定集成电路之间的通信的方法和装置
公开(公告)号：US20160226491A1
公开(公告)日：2016-08-04
申请号：US14612076
申请日：2015-02-02
申请人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
发明人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
IPC分类号： H03K19/0175 , H03K19/177 , H03K19/02
CPC分类号： H03K19/017581 , H03K19/02 , H03K19/17736
摘要： A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.
摘要翻译：公开了一种包含专用集成电路（“ASIC”）和现场可编程门阵列（“FPGA”）的逻辑处理装置，能够自动连接ASIC和FPGA。逻辑处理装置在一个方面包括相位调整电路，ASIC和可配置逻辑电路（“CLC”），其中CLC可以是FPGA。虽然ASIC能够根据ASIC时钟域执行特定功能，但是CLC能够根据FPGA时钟域执行可编程逻辑功能。相位调整电路用于根据ASIC时钟域和FPGA时钟域来自动促进ASIC和CLC之间的通信。

2. 发明申请

US20180062654A9 METHOD AND APPARATUS FOR FACILITATING COMMUNICATION BETWEEN PROGRAMMABLE LOGIC CIRCUIT AND APPLICATION SPECIFIC INTEGRATED CIRCUIT WITH CLOCK ADJUSTMENT 审中-公开
公开(公告)号：US20180062654A9
公开(公告)日：2018-03-01
申请号：US14612076
申请日：2015-02-02
申请人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
发明人： Kai Keung Chan , David Tsang , Shian-Jiun Fu , Chao-Chiang Chen
IPC分类号： H03K19/0175 , H03K19/02 , H03K19/177
CPC分类号： H03K19/017581 , H03K19/02 , H03K19/17736
摘要： A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (“CLC”) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

3. 发明授权

US06870760B2 Method and system for performing readout utilizing a self reference scheme 失效
标题翻译：使用自身参考方案执行读出的方法和系统
公开(公告)号：US06870760B2
公开(公告)日：2005-03-22
申请号：US10688290
申请日：2003-10-16
申请人： David Tsang
发明人： David Tsang
IPC分类号： G11C11/16 , G11C11/00
CPC分类号： G11C11/16 , G11C11/1673
摘要： A method and system for reading a magnetic memory including a plurality of magnetic elements is disclosed. The method and system include determining a first resistance of at least one of the plurality of magnetic elements. The method and system also include applying a disturb magnetic field to the magnetic element(s) and determining a second resistance of the magnetic element(s) while the disturb magnetic field is applied. The method and system further include comparing the first resistance to the second resistance. Consequently, the state(s) of the magnetic element(s) can be determined without the use of a separate reference element.
摘要翻译：公开了一种用于读取包括多个磁性元件的磁存储器的方法和系统。该方法和系统包括确定多个磁性元件中的至少一个的第一电阻。所述方法和系统还包括在施加扰动磁场时向磁性元件施加干扰磁场并确定磁性元件的第二电阻。所述方法和系统还包括将第一电阻与第二电阻进行比较。因此，可以在不使用单独的参考元件的情况下确定磁性元件的状态。

4. 发明授权

US06870759B2 MRAM array with segmented magnetic write lines 失效
标题翻译：具有分段磁写行的MRAM阵列
公开(公告)号：US06870759B2
公开(公告)日：2005-03-22
申请号：US10646455
申请日：2003-08-21
申请人： David Tsang
发明人： David Tsang
IPC分类号： G11C11/15 , G11C11/16 , G11C11/02
CPC分类号： G11C11/16 , G11C11/15
摘要： A magnetic random access memory (MRAM) array and method for making the MRAM array are disclosed. The MRAM array includes magnetic storage cells, global word lines, magnetic word lines, read bit lines, selection devices, and write bit lines. Each magnetic word line has segments. Each segment is coupled with the global word line(s) such that each segment is separately selectable. Each segment is also coupled to a portion of the magnetic storage cells. The read bit lines are oriented at an angle with respect to the magnetic word lines. The read bit lines are coupled with the magnetic cells through the selection devices. The write bit lines are substantially parallel to the read bit lines. Preferably, the magnetic word lines include soft magnetic materials and are coupled to each magnetic storage cell through a thin, nonmagnetic layer. To reduce interference from currents in global word lines, the global word lines are also substantially parallel to the magnetic word lines.
摘要翻译：公开了磁性随机存取存储器（MRAM）阵列和用于制造MRAM阵列的方法。 MRAM阵列包括磁存储单元，全局字线，磁字线，读位线，选择装置和写位线。每个磁性字线都有段。每个段与全局字线耦合，使得每个段是可单独选择的。每个段也耦合到磁存储单元的一部分。读取位线相对于磁性字线成一定角度。读位线通过选择装置与磁细胞耦合。写位线基本上平行于读位线。优选地，磁性字线包括软磁性材料，并且通过薄的非磁性层耦合到每个磁性存储单元。为了减少全局字线中电流的干扰，全局字线也基本上平行于磁性字线。

5. 发明授权

US06982916B2 Method and system for providing temperature dependent programming for magnetic memories 失效
标题翻译：用于为磁存储器提供温度依赖编程的方法和系统
公开(公告)号：US06982916B2
公开(公告)日：2006-01-03
申请号：US10778781
申请日：2004-02-12
申请人： David Tsang
发明人： David Tsang
IPC分类号： G11C7/04
CPC分类号： G11C11/16
摘要： A method and system for programming a magnetic memory including a plurality of magnetic elements is disclosed. The method and system include sensing a temperature of the magnetic memory and providing an indication of the temperature of the magnetic memory. The method and system also include providing a current that is based on the indication of temperature of the magnetic memory. The current is temperature dependent and can be used in programming at least a portion of the magnetic elements without the addition of a separately generated current. In addition, the method and system include carrying for at least a portion of the plurality of magnetic elements. The temperature is preferably sensed by at least one temperature sensor, while the current is preferably provided by a current source coupled with the temperature sensor(s).
摘要翻译：公开了一种用于对包括多个磁性元件的磁存储器进行编程的方法和系统。该方法和系统包括感测磁存储器的温度并提供磁存储器的温度的指示。该方法和系统还包括提供基于磁存储器的温度指示的电流。电流是温度依赖性的，并且可以用于编程至少一部分磁性元件而不增加单独产生的电流。此外，该方法和系统包括承载多个磁性元件的至少一部分。温度优选地由至少一个温度传感器感测，而电流优选地由与温度传感器耦合的电流源提供。

6. 发明授权

US06963500B2 Magnetic tunneling junction cell array with shared reference layer for MRAM applications 失效
标题翻译：具有用于MRAM应用的共享参考层的磁隧道结电池阵列
公开(公告)号：US06963500B2
公开(公告)日：2005-11-08
申请号：US10781131
申请日：2004-02-17
申请人： David Tsang
发明人： David Tsang
IPC分类号： G11C11/15 , G11C11/14
CPC分类号： G11C11/15
摘要： A method and system for providing a magnetic memory is disclosed. The method and system include providing a plurality of magnetic elements and a plurality of reference layers. Each of the magnetic elements includes a free layer and a spacer layer. Each of the reference layers is coupled with a corresponding portion of the magnetic elements. The reference layers are ferromagnetic. A portion of each reference layer functions as at least a portion of a pinned layer for each of the corresponding portion of the magnetic elements. The portion of each of the plurality of reference layers also functions as a write line for the corresponding portion of the plurality of magnetic elements. The spacer layer resides between the free layer of each of the plurality of magnetic elements and the reference layer.
摘要翻译：公开了一种用于提供磁存储器的方法和系统。该方法和系统包括提供多个磁性元件和多个参考层。每个磁性元件包括自由层和间隔层。每个参考层与磁性元件的对应部分耦合。参考层是铁磁性的。每个参考层的一部分用作磁性元件的相应部分中的每一个的被钉扎层的至少一部分。多个参考层中的每一个的部分也用作多个磁性元件的对应部分的写入线。间隔层位于多个磁性元件中的每一个的自由层和参考层之间。

7. 发明授权

US06933550B2 Method and system for providing a magnetic memory having a wrapped write line 失效
标题翻译：用于提供具有包裹的写入线的磁存储器的方法和系统
公开(公告)号：US06933550B2
公开(公告)日：2005-08-23
申请号：US10781478
申请日：2004-02-17
申请人： David Tsang
发明人： David Tsang
IPC分类号： G11C11/15 , H01L31/119 , G11C7/02
CPC分类号： G11C11/15
摘要： A method and system for providing magnetic memory are disclosed. The method and system include providing a plurality of magnetic memory elements and providing at least one wrapped write line. Each wrapped write line includes a bottom write line and a top write line electrically connected to the bottom write line. The bottom write line resides below a portion of the plurality of magnetic elements, while the top write resides above the portion of the plurality of magnetic elements. The bottom write line carries a first current in a first direction, while the top write line carries a second current in a second direction opposite to the first direction.
摘要翻译：公开了一种用于提供磁存储器的方法和系统。该方法和系统包括提供多个磁存储器元件并且提供至少一个封装的写入线。每个封装的写行包括底部写入线和电连接到底部写入线的顶部写入线。底部写入线位于多个磁性元件的一部分下方，而顶部写入位于多个磁性元件的部分之上。底部写入线在第一方向上承载第一电流，而顶部写入线在与第一方向相反的第二方向上承载第二电流。

8. 发明授权

US06812538B2 MRAM cells having magnetic write lines with a stable magnetic state at the end regions 失效
标题翻译：具有在端部区域具有稳定磁状态的磁写入线的MRAM单元
公开(公告)号：US06812538B2
公开(公告)日：2004-11-02
申请号：US10669216
申请日：2003-09-23
申请人： David Tsang
发明人： David Tsang
IPC分类号： H01L2982
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/15
摘要： A method and system for providing and using a magnetic memory are disclosed. The magnetic memory includes a plurality of magnetic memory cells, a plurality of magnetic write lines and a plurality of magnetic biasing structures. The plurality of magnetic write lines have a plurality of end regions. The plurality of magnetic biasing structures coupled to the plurality of end regions of the plurality of magnetic write lines.
摘要翻译：公开了一种用于提供和使用磁存储器的方法和系统。磁存储器包括多个磁存储单元，多个磁写线和多个磁偏置结构。多个磁写入线具有多个端部区域。多个磁偏置结构耦合到多个磁写入线的多个端部区域。

9. 发明申请

US20080101241A1 Ethernet OAM at intermediate nodes in a PBT network 审中-公开
标题翻译：以太网OAM在PBT网络的中间节点
公开(公告)号：US20080101241A1
公开(公告)日：2008-05-01
申请号：US11724981
申请日：2007-03-16
申请人： Dinesh Mohan , Christopher Monti , Piotr Romanus , David Tsang , Michael Chen
发明人： Dinesh Mohan , Christopher Monti , Piotr Romanus , David Tsang , Michael Chen
IPC分类号： H04L12/26
CPC分类号： H04L41/0213 , H04L12/4641
摘要： OAM may be implemented at an intermediate node on a PBT trunk in an Ethernet network by causing OAM frames to be addressed to the PBT trunk endpoint but causing the OAM frames to carry an indicia (Ether-type, OpCode, TLV value or combination of these and other fields) that the OAM frames are intended to be used for intermediate node OAM functions. The Ether-type, OpCode, and TLV values may be standardized values, or vendor specific values such as OpCode=51 or TLV=31 may be used. Addressing the OAM frames to the PBT trunk end point enables the OAM frames to follow the PBT trunk through the network. The OAM indicia signals to the intermediate nodes that the OAM frames are intended to be used to perform an intermediate node OAM function. The OAM frames may contain reverse trunk information to prevent the intermediate nodes from being required to store correlation between forward and reverse PBT trunks.
摘要翻译： OAM可以通过使OAM帧被寻址到PBT中继端点而实现在以太网网络中的PBT中继的中间节点上，但是导致OAM帧携带标记（以太类型，OpCode，TLV值或这些的组合和其他字段），OAM帧旨在用于中间节点OAM功能。以太类型，OpCode和TLV值可以是标准化值，或者可以使用诸如OpCode = 51或TLV = 31的供应商特定值。将OAM帧寻址到PBT中继端点使得OAM帧能够通过网络跟随PBT中继。 OAM标记向中间节点发信号通知OAM帧旨在用于执行中间节点OAM功能。 OAM帧可能包含反向中继信息，以防止中间节点需要存储正向和反向PBT中继线之间的相关性。

10. 发明授权

US06940749B2 MRAM array with segmented word and bit lines 失效
标题翻译：具有分段字和位线的MRAM阵列
公开(公告)号：US06940749B2
公开(公告)日：2005-09-06
申请号：US10669481
申请日：2003-09-23
申请人： David Tsang
发明人： David Tsang
IPC分类号： G11C7/18 , G11C8/14 , G11C11/15 , G11C11/14
CPC分类号： G11C8/14 , G11C7/18 , G11C11/15
摘要： A method and system for providing and using a magnetic random access memory (MRAM) array are disclosed. The method and system include providing magnetic storage cells, global word lines and global word line segments, of global bit lines and bit line segments, and selection devices. Each word line segment is coupled with at least one global word line such that the word line segments are selectable. Each word line segment is also coupled to a portion of the magnetic storage cells. Each bit line segment is coupled with at least one global bit line such the bit line segments are selectable. Each bit line segment resides in proximity to and is used to write to a portion of the magnetic storage cells. The bit line segments and the word line segments are coupled with and selectable using the plurality of selection devices.
摘要翻译：公开了一种用于提供和使用磁随机存取存储器（MRAM）阵列的方法和系统。该方法和系统包括提供全局位线和位线段的磁存储单元，全局字线和全局字线段以及选择装置。每个字线段与至少一个全局字线耦合，使得字线段是可选择的。每个字线段也耦合到磁存储单元的一部分。每个位线段与至少一个全局位线耦合，使得位线段是可选择的。每个位线段驻留在磁存储单元的一部分附近并被用于写入磁存储单元的一部分。位线段和字线段与多个选择装置耦合并可选择。

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