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1. 发明申请

US20090060068A1 Method and apparatus for bit interleaving and deinterleaving in wireless communication systems 有权
标题翻译：用于无线通信系统中的比特交织和解交织的方法和装置
公开(公告)号：US20090060068A1
公开(公告)日：2009-03-05
申请号：US12011870
申请日：2008-01-30
申请人： Debashis Goswami , Geethanjali Rajegowda
发明人： Debashis Goswami , Geethanjali Rajegowda
IPC分类号： H03M13/27 , H04L29/02 , G01F11/00
CPC分类号： H03M13/2789 , H03M13/275 , H03M13/276 , H03M13/6508 , H03M13/6527 , H03M13/6544 , H03M13/655 , H03M13/6561 , H04L1/0071
摘要： Disclosed herein is a method and system for interleaving and deinterleaving of data bits in wireless data communications. Interleaving is performed as a single stage parallel operation using a single standard memory block. The disclosed method and system is capable of implementing different interleaving techniques, individually, or as a combination thereof. The disclosed system comprises a plurality of multiplexers, a standard memory block, read and write buses, control block, and a lookup table. The contents of the lookup table are generated based on an interleaving function. The data bits from the input bus and bits from the read bus of the memory are inputted to the plurality of multiplexers. Based on the lookup table's contents the multiplexers are switched to parallelly permute the input data bits and read bits from the read bus. The permuted data bits are in an interleaved sequence.
摘要翻译：这里公开了一种用于无线数据通信中的数据比特的交织和解交织的方法和系统。使用单个标准存储器块进行交织作为单级并行操作。所公开的方法和系统能够单独地或作为其组合来实现不同的交织技术。所公开的系统包括多个复用器，标准存储器块，读取和写入总线，控制块和查找表。基于交织功能生成查找表的内容。来自输入总线的数据位和存储器的读总线的位被输入到多个复用器。基于查找表的内容，多路复用器被切换以并行地排列输入数据位并从读总线读取位。置换的数据位是交错序列。

2. 发明授权

US07886203B2 Method and apparatus for bit interleaving and deinterleaving in wireless communication systems 有权
标题翻译：用于无线通信系统中的比特交织和解交织的方法和装置
公开(公告)号：US07886203B2
公开(公告)日：2011-02-08
申请号：US12011870
申请日：2008-01-30
申请人： Debashis Goswami , Geethanjali Rajegowda
发明人： Debashis Goswami , Geethanjali Rajegowda
IPC分类号： G11C29/00 , H03M13/03
CPC分类号： H03M13/2789 , H03M13/275 , H03M13/276 , H03M13/6508 , H03M13/6527 , H03M13/6544 , H03M13/655 , H03M13/6561 , H04L1/0071
摘要： Disclosed herein is a method and system for interleaving and deinterleaving of data bits in wireless data communications. Interleaving is performed as a single stage parallel operation using a single standard memory block. The disclosed method and system is capable of implementing different interleaving techniques, individually, or as a combination thereof. The disclosed system comprises a plurality of multiplexers, a standard memory block, read and write buses, control block, and a lookup table. The contents of the lookup table are generated based on an interleaving function. The data bits from the input bus and bits from the read bus of the memory are inputted to the plurality of multiplexers. Based on the lookup table's contents the multiplexers are switched to parallelly permute the input data bits and read bits from the read bus. The permuted data bits are in an interleaved sequence.
摘要翻译：这里公开了一种用于无线数据通信中的数据比特的交织和解交织的方法和系统。使用单个标准存储器块进行交织作为单级并行操作。所公开的方法和系统能够单独地或作为其组合来实现不同的交织技术。所公开的系统包括多个复用器，标准存储器块，读取和写入总线，控制块和查找表。基于交织功能生成查找表的内容。来自输入总线的数据位和存储器的读总线的位被输入到多个复用器。基于查找表的内容，多路复用器被切换以并行地排列输入数据位并从读总线读取位。置换的数据位是交错序列。

3. 发明申请

US20070226285A1 A HIGH SPEED FFT HARDWARE ARCHITECTURE FOR AN OFDM PROCESSOR 有权
标题翻译：用于OFDM处理器的高速FFT硬件架构
公开(公告)号：US20070226285A1
公开(公告)日：2007-09-27
申请号：US11277366
申请日：2006-03-24
申请人： Debashis Goswami , Gagandeep Singh
发明人： Debashis Goswami , Gagandeep Singh
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , H04L27/265
摘要： A novel technique for providing high speed FFT architecture for OFDM processors that reduces silicon area while maintaining the high speed requirement. In one example embodiment, this is accomplished by pipelined and/or sequential implementation of two or more FFT stages so that each stage performs a small portion of the FFT.
摘要翻译：一种用于为OFDM处理器提供高速FFT架构的新技术，可以在保持高速度要求的同时降低硅面积。在一个示例实施例中，这通过流水线和/或顺序实现两个或更多个FFT级来实现，使得每个级执行FFT的一小部分。

4. 发明授权

US07702713B2 High speed FFT hardware architecture for an OFDM processor 有权
标题翻译：用于OFDM处理器的高速FFT硬件架构
公开(公告)号：US07702713B2
公开(公告)日：2010-04-20
申请号：US11277366
申请日：2006-03-24
申请人： Debashis Goswami , Gagandeep Singh
发明人： Debashis Goswami , Gagandeep Singh
IPC分类号： G06F17/14
CPC分类号： G06F17/142 , H04L27/265
摘要： A novel technique for providing high speed FFT architecture for OFDM processors that reduces silicon area while maintaining the high speed requirement. In one example embodiment, this is accomplished by pipelined and/or sequential implementation of two or more FFT stages so that each stage performs a small portion of the FFT.
摘要翻译：一种用于为OFDM处理器提供高速FFT架构的新技术，可以在保持高速度要求的同时降低硅面积。在一个示例实施例中，这通过流水线和/或顺序实现两个或更多个FFT级来实现，使得每个级执行FFT的一小部分。

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