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1. 发明授权

US07777541B1 Charge pump circuit and method for phase locked loop 有权
标题翻译：电荷泵电路和锁相环路方法
公开(公告)号：US07777541B1
公开(公告)日：2010-08-17
申请号：US11701215
申请日：2007-02-01
申请人： Galen E. Stansell , Timothy Wright
发明人： Galen E. Stansell , Timothy Wright
IPC分类号： H03L7/06
CPC分类号： H03L7/0891
摘要： A charge pump circuit can include a pump-up circuit having a first disable switch coupled between a pump-up output node and a first power supply node that is enabled and then disabled in response to a source current path between the pump-up node and a second power supply node being disabled, and a source off switch coupled in series with the first disable switch that is enabled in response to the source current path being disabled. The charge pump circuit can also include a pump-down circuit having a second disable switch coupled between a pump-down output node and the second power supply node that is enabled and then disabled in response to a sink current path between the pump-down node and a first power supply node being disabled. A sink off switch can be coupled in series with the second disable switch that is enabled in response to the sink current path being disabled.
摘要翻译：电荷泵电路可以包括泵浦电路，其具有耦合在泵浦输出节点和第一电源节点之间的第一禁用开关，其被启用，然后响应于泵浦节点和被禁用的第二电源节点以及与所述第一禁用开关串联耦合的源关闭开关，所述第一禁用开关响应于所述源电流路径被禁用而被启用。电荷泵电路还可以包括抽水电路，其具有耦合在降压输出节点和第二电源节点之间的第二禁用开关，所述第二禁用开关响应于所述抽水节点并且第一电源节点被禁用。汇流开关可以与响应于吸收电流路径被禁用而被使能的第二禁用开关串联耦合。

2. 发明授权

US06373306B1 Clock generator with programmable two-tone modulation for EMI reduction 有权
标题翻译：具有可编程双音调制的时钟发生器，用于降低EMI
公开(公告)号：US06373306B1
公开(公告)日：2002-04-16
申请号：US09689492
申请日：2000-10-12
申请人： Eric N. Mann , Galen E. Stansell , Monte F. Mar
发明人： Eric N. Mann , Galen E. Stansell , Monte F. Mar
IPC分类号： H03L700
CPC分类号： H03L7/197
摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal that ramps between a first and second frequency in response to (i) a first control signal, (ii) a second control signal, and (iii) a first reference signal. The second circuit may be configured to generate the first and second control signals in response to a third control signal having a third frequency. The third frequency may reduce electromagnetic interference generated by the first circuit.
摘要翻译：一种包括第一电路和第二电路的装置。第一电路可以被配置为响应于（i）第一控制信号，（ii）第二控制信号和（iii）第一参考信号而产生在第一和第二频率之间斜坡的输出信号。第二电路可以被配置为响应于具有第三频率的第三控制信号而产生第一和第二控制信号。第三频率可以减小由第一电路产生的电磁干扰。

3. 发明授权

US5886582A Enabling clock signals with a phase locked loop (PLL) lock detect circuit 失效
标题翻译：使用锁相环（PLL）锁定检测电路启用时钟信号
公开(公告)号：US5886582A
公开(公告)日：1999-03-23
申请号：US693735
申请日：1996-08-07
申请人： Galen E. Stansell
发明人： Galen E. Stansell
IPC分类号： G06F1/10 , H03L7/07 , H03L7/089 , H03L7/095 , H03K5/135
CPC分类号： H03L7/07 , G06F1/10 , H03L7/095 , H03L7/089 , Y10S331/02
摘要： A circuit for enabling and disabling generation of an output clock signal is disclosed. The circuit includes a PLL lock detect circuit that generates an active lock control signal when an output reference signal of a phase lock loop (PLL) circuit is phase locked relative to an input reference signal to the PLL. The output reference signal of the PLL, and the lock signal from the lock detect circuit, are both provided to a clock enable circuit. The clock enable circuit includes a negative edge-triggered D-type flip-flop and a two-input AND gate. The lock signal is applied to the D-input of the flip-flop, while the clock signal is applied to the clock input of the flip-flop. The lock signal is generated asynchronously relative to the input clock signal. Therefore, the flip-flop samples the lock signal on each falling edge of the clock signal so as to synchronize the lock signal relative to the input clock signal. The sampled lock signal, and the input clock signal (formed from the PLL output reference signal) are provided on respective input terminals of the AND gate. The output of the AND gate defines the output clock signal.
摘要翻译：公开了一种用于启用和禁用产生输出时钟信号的电路。该电路包括PLL锁定检测电路，当锁相环（PLL）电路的输出参考信号相对于PLL的输入参考信号相位锁定时，产生一个主动锁定控制信号。 PLL的输出参考信号和来自锁定检测电路的锁定信号都被提供给时钟使能电路。时钟使能电路包括负沿触发D型触发器和双输入与门。锁定信号被施加到触发器的D输入，而时钟信号被施加到触发器的时钟输入。锁定信号相对于输入时钟信号异步产生。因此，触发器在时钟信号的每个下降沿采样锁定信号，以使锁定信号相对于输入时钟信号同步。采样锁定信号和输入时钟信号（由PLL输出参考信号形成）设置在与门的各个输入端上。与门的输出定义输出时钟信号。

4. 发明授权

US06798297B1 Method and apparatus for converging a control loop 有权
标题翻译：用于收敛控制回路的方法和装置
公开(公告)号：US06798297B1
公开(公告)日：2004-09-28
申请号：US10301768
申请日：2002-11-20
申请人： King H. Kwan , Galen E. Stansell
发明人： King H. Kwan , Galen E. Stansell
IPC分类号： H03L708
CPC分类号： H03L7/10 , H03L7/093 , H03L7/095 , H03L7/099
摘要： In one embodiment, a control loop in an electrical circuit includes a variable feed-forward circuit configured to determine a setting of a variable oscillator that would result in a frequency of a first signal approximating a frequency of a second signal. The setting may be used to control the variable oscillator at a time when a phase error between the first signal and the second signal is negligibly small (e.g., substantially zero), thus allowing for relatively short loop convergence time.
摘要翻译：在一个实施例中，电路中的控制回路包括可变前馈电路，其被配置为确定将导致接近第二信号的频率的第一信号的频率的可变振荡器的设置。在第一信号和第二信号之间的相位误差可忽略不计（例如基本上为零）的时刻，该设置可用于控制可变振荡器，从而允许相对较短的环路收敛时间。

5. 发明授权

US06559726B1 Multi-modulus counter in modulated frequency synthesis 有权
标题翻译：调制频率合成中的多模计数器
公开(公告)号：US06559726B1
公开(公告)日：2003-05-06
申请号：US09999743
申请日：2001-10-31
申请人： Galen E. Stansell
发明人： Galen E. Stansell
IPC分类号： H03L718
CPC分类号： H03C3/0933 , H03C3/0925 , H03K23/665 , H03K23/667 , H03L7/193 , H03L7/197
摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to a reference input and a feedback signal. The second circuit may be configured to generate the feedback signal according to a plurality of moduli in response to the output signal, a first control signal and a second control signal. The frequency of the output signal may be modulated in response to the second control signal.
摘要翻译：一种包括第一电路和第二电路的装置。第一电路可以被配置为响应于参考输入和反馈信号而产生输出信号。第二电路可以被配置为响应于输出信号，第一控制信号和第二控制信号，根据多个模数产生反馈信号。可以响应于第二控制信号来调制输出信号的频率。

6. 发明授权

US06271702B1 Clock circuit for generating a delay 失效
标题翻译：用于产生延迟的时钟电路
公开(公告)号：US06271702B1
公开(公告)日：2001-08-07
申请号：US09105329
申请日：1998-06-25
申请人： Galen E. Stansell
发明人： Galen E. Stansell
IPC分类号： G06F104
CPC分类号： G06F1/06 , H03K5/15
摘要： A delay generation circuit comprising (i) a circuit configured to generate a reference clock signal having a period, (ii) a divide circuit and (iii) an output circuit. The divide circuit may be configured to generate a first divided clock signal and a second divided clock signal in response to said reference clock signal. The output circuit may be configured to generate (i) a first output clock signal and (ii) a second output clock signal in response to (i) the first and second divided clock signals and (ii) the reference clock signal. The second output clock signal may have a delay with respect to the first output clock signal. The delay may be (i) a multiple of or (ii) a fraction of the period of the reference clock signal.
摘要翻译：一种延迟生成电路，包括：（i）电路，被配置为产生具有周期的参考时钟信号，（ii）除法电路和（iii）输出电路。分频电路可以被配置为响应于所述参考时钟信号产生第一分频时钟信号和第二分频时钟信号。响应于（i）第一和第二分频时钟信号和（ii）参考时钟信号，输出电路可以被配置为产生（i）第一输出时钟信号和（ii）第二输出时钟信号。第二输出时钟信号可以具有相对于第一输出时钟信号的延迟。延迟可以是（i）参考时钟信号的周期的一部分或（ii）的一部分。

7. 发明授权

US07598794B1 Well bias architecture for integrated circuit device 有权
标题翻译：用于集成电路器件的良好偏置架构
公开(公告)号：US07598794B1
公开(公告)日：2009-10-06
申请号：US11904246
申请日：2007-09-25
申请人： Galen E. Stansell , King Eric Kwan , Xiaolin Ouyang
发明人： Galen E. Stansell , King Eric Kwan , Xiaolin Ouyang
IPC分类号： H03K3/01
CPC分类号： H03K19/00315 , H03K19/1732 , H03K2217/0018
摘要： Disclosed is a high voltage switch circuit that can include a first well bias switch configured to track the greater of an input voltage and a supply voltage, a voltage comparator configurable to compare the input voltage to a predetermined reference voltage, and a second well bias switch having a control input coupled to an output of the comparator.
摘要翻译：公开了一种高压开关电路，其可以包括构造成跟踪输入电压和电源电压较大的第一阱偏置开关，可配置为将输入电压与预定参考电压进行比较的电压比较器，以及第二阱偏置开关具有耦合到比较器的输出的控制输入。

8. 发明授权

US07426142B1 Device and method for sensing programming status of non-volatile memory elements 有权
标题翻译：用于感测非易失性存储器元件的编程状态的装置和方法
公开(公告)号：US07426142B1
公开(公告)日：2008-09-16
申请号：US11415694
申请日：2006-05-01
申请人： Galen E. Stansell , Tomasz Cewe
发明人： Galen E. Stansell , Tomasz Cewe
IPC分类号： G11C16/06
CPC分类号： G11C17/18 , G11C17/14 , G11C29/00 , G11C2029/5002 , G11C2029/5006
摘要： A test circuit can test a status of a group of non-volatile elements. A current flowing to the group of non-volatile elements can be compared against a reference value. If the current is determined to be outside of a predetermined range, the non-volatile elements can be determined to be programmed. In particular embodiments, non-volatile elements can be sections of differential one-time programmable anti-fuse latch memory elements.
摘要翻译：测试电路可以测试一组非易失性元件的状态。可以将流向该组非易失性元件的电流与参考值进行比较。如果确定电流在预定范围之外，则可以确定非易失性元件被编程。在特定实施例中，非易失性元件可以是差分一次可编程反熔丝闩锁存储元件的部分。

9. 发明授权

US06674332B1 Robust clock circuit architecture 有权
标题翻译：可靠的时钟电路架构
公开(公告)号：US06674332B1
公开(公告)日：2004-01-06
申请号：US10236475
申请日：2002-09-06
申请人： John J. Wunner , Galen E. Stansell
发明人： John J. Wunner , Galen E. Stansell
IPC分类号： H03L706
CPC分类号： H03L7/148 , H03L7/235
摘要： In one embodiment, a first circuit is configured to receive an input reference signal and a feedback signal, and present a reference clock signal based on a difference (e.g., phase difference) between the input reference signal and the feedback signal. The first circuit is further configured to present the reference clock signal even when the reference signal is disrupted. A frequency divider may be employed to scale the frequency of the feedback signal. The reference clock signal may be presented to another circuit to generate one or more output clock signals that are phase-locked to the reference clock signal, for example.
摘要翻译：在一个实施例中，第一电路被配置为接收输入参考信号和反馈信号，并且基于输入参考信号和反馈信号之间的差（例如，相位差）呈现参考时钟信号。第一电路还被配置为即使当参考信号中断时也呈现参考时钟信号。可以使用分频器来缩放反馈信号的频率。例如，可以将参考时钟信号呈现给另一电路以产生锁相到参考时钟信号的一个或多个输出时钟信号。

10. 发明授权

US06175259B1 Clock generator with programmable two-tone modulation for EMI reduction 有权
标题翻译：具有可编程双音调制的时钟发生器，用于降低EMI
公开(公告)号：US06175259B1
公开(公告)日：2001-01-16
申请号：US09246981
申请日：1999-02-09
申请人： Eric N. Mann , Galen E. Stansell , Monte F. Mar
发明人： Eric N. Mann , Galen E. Stansell , Monte F. Mar
IPC分类号： H03L700
CPC分类号： H03L7/197
摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal that ramps between a first and second frequency in response to (i) a first control signal, (ii) a second control signal, and (iii) a first reference signal. The second circuit may be configured to generate the first and second control signals in response to a third control signal having a third frequency. The third frequency may reduce electromagnetic interference generated by the first circuit.
摘要翻译：一种包括第一电路和第二电路的装置。第一电路可以被配置为响应于（i）第一控制信号，（ii）第二控制信号和（iii）第一参考信号而产生在第一和第二频率之间斜坡的输出信号。第二电路可以被配置为响应于具有第三频率的第三控制信号来产生第一和第二控制信号。第三频率可以减小由第一电路产生的电磁干扰。

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