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1. 发明申请

US20120275210A1 NON-VOLATILE STORAGE SYSTEM WITH DUAL BLOCK PROGRAMMING 有权
标题翻译：具有双块编程的非易失存储系统
公开(公告)号：US20120275210A1
公开(公告)日：2012-11-01
申请号：US13095779
申请日：2011-04-27
申请人： Tianhong Yan , Tz-yi Liu , Roy E. Scheuerlein
发明人： Tianhong Yan , Tz-yi Liu , Roy E. Scheuerlein
IPC分类号： G11C11/00 , G11C8/08 , G11C7/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0023 , G11C13/003 , G11C2213/71 , G11C2213/73 , G11C2213/77
摘要： A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non-volatile storage elements, a plurality of bit lines connected to the blocks of non-volatile storage elements, multiple sets of word lines drivers such that each set of word line drivers is positioned between two adjacent blocks for driving word lines connected to the two adjacent blocks, global data lines, local data lines in selective communication with the bit lines, one or more selection circuits that selectively connect the global data lines to selected local data lines and connect unselected local data lines to one or more unselected bit line signals and control circuitry in communication with the one or more selection circuits and the global data lines. The control circuitry concurrently programs non-volatile storage elements of two adjacent blocks by applying programming signals on word lines connected to the two adjacent blocks and applying programming signals on appropriate bit lines via the global data lines and the one or more selection circuits.
摘要翻译：公开了一种非易失性存储系统，其包括多个非易失性存储元件块，连接到非易失性存储元件的块的多个字线，使得每个字线连接到非易失性存储元件的相邻块存储元件，连接到非易失性存储元件块的多个位线，多组字线驱动器，使得每组字线驱动器位于两个相邻块之间，用于驱动连接到两个相邻块的字线，全局数据线，与位线选择性通信的本地数据线，一个或多个选择电路，其选择性地将全局数据线连接到选定的本地数据线，并将未选择的本地数据线连接到一个或多个未选位线信号和控制电路与一个或多个选择电路和全局数据线通信。控制电路通过在连接到两个相邻块的字线上应用编程信号并经由全局数据线和一个或多个选择电路在适当的位线上施加编程信号来同时对两个相邻块的非易失性存储元件进行编程。

2. 发明申请

US20120236663A1 PROGRAM CYCLE SKIP 有权
标题翻译：程序循环跳
公开(公告)号：US20120236663A1
公开(公告)日：2012-09-20
申请号：US13488600
申请日：2012-06-05
申请人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
发明人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0007 , G11C13/0061 , G11C17/165 , G11C17/18 , G11C2013/0076 , G11C2013/0085 , G11C2213/71
摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.
摘要翻译：非易失性存储系统包括在编程页面（或其他单元）数据时跳过编程周期的技术。在对页面（或其他单元）数据的当前子集进行编程时，系统将评估页面（或其他单元）的下一个子集是否应编程为非易失性存储元素或跳过。不应被跳过的页面（或其他单元）的子集被编程到非易失性存储元件中。一些实施例包括将适当数据传送到临时锁存器/寄存器，以准备编程，同时评估是编程还是跳过编程。

3. 发明申请

US20110141788A1 PAGE REGISTER OUTSIDE ARRAY AND SENSE AMPLIFIER INTERFACE 有权
标题翻译：页面寄存器外部阵列和感测放大器接口
公开(公告)号：US20110141788A1
公开(公告)日：2011-06-16
申请号：US12638719
申请日：2009-12-15
申请人： Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Yuheng Zhang , Tz-Yi Liu , Luca Fasoli
发明人： Gopinath Balakrishnan , Jeffrey Koon Yee Lee , Yuheng Zhang , Tz-Yi Liu , Luca Fasoli
IPC分类号： G11C5/02 , G11C11/00 , G11C7/18
CPC分类号： G11C5/025 , B82Y10/00 , G11C5/02 , G11C13/0002 , G11C13/0007 , G11C13/025 , G11C17/16 , G11C2213/19 , G11C2213/32 , G11C2213/33 , G11C2213/34 , G11C2213/71
摘要： A non-volatile storage device includes a substrate, a monolithic three-dimensional memory array of non-volatile storage elements arranged above a portion of the substrate, a plurality of sense amplifiers in communication with the non-volatile storage elements, a plurality of temporary storage devices in communication with the sense amplifiers, a page register in communication with the temporary storage devices, and one or more control circuits. The one or more control circuits are in communication with the page register, the temporary storage devices and the sense amplifiers. The sense amplifiers are arranged on the substrate underneath the monolithic three-dimensional memory array. The temporary storage devices are arranged on the substrate underneath the monolithic three-dimensional memory array. The page register is arranged on the substrate in an area that is not underneath the monolithic three-dimensional memory array. Data read from the non-volatile storage elements by the sense amplifiers is transferred to the temporary storage devices and then to the page register in response to the one or more control circuits. Data to be programmed into the non-volatile storage elements is transferred to the temporary storage devices from the page register in response to the one or more control circuits.
摘要翻译：非易失性存储装置包括衬底，布置在衬底的一部分上方的非易失性存储元件的单片三维存储器阵列，与非易失性存储元件通信的多个读出放大器，多个临时与读出放大器通信的存储装置，与临时存储装置通信的页寄存器，以及一个或多个控制电路。一个或多个控制电路与页寄存器，临时存储设备和读出放大器通信。读出放大器布置在单片三维存储器阵列下方的衬底上。临时存储装置布置在单片三维存储器阵列下面的衬底上。页面寄存器在不在单片三维存储器阵列下方的区域中布置在基板上。由感测放大器从非易失性存储元件读取的数据响应于一个或多个控制电路传送到临时存储设备，然后传送到页寄存器。要编程到非易失性存储元件中的数据响应于一个或多个控制电路从页寄存器传送到临时存储设备。

4. 发明授权

US06842380B2 Method and apparatus for erasing memory 有权
标题翻译：擦除存储器的方法和装置
公开(公告)号：US06842380B2
公开(公告)日：2005-01-11
申请号：US10228597
申请日：2002-08-27
申请人： Vinod Lakhani , Tz-Yi Liu
发明人： Vinod Lakhani , Tz-Yi Liu
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/16
摘要： The present invention provides a method and apparatus for erasing memory blocks. The apparatus includes a first plurality of memory cells formed in a substrate and a second plurality of memory cells formed in the substrate. The apparatus further includes a bias circuit adapted to provide an erasing voltage differential to the first plurality of memory cells and a compensating voltage differential to the second plurality of memory cells, wherein the erasing voltage differential is larger than the compensating voltage differential.
摘要翻译：本发明提供一种擦除存储块的方法和装置。该装置包括形成在基板中的第一多个存储单元和形成在基板中的第二多个存储单元。该装置还包括偏置电路，其适于向第一多个存储单元提供擦除电压差，以及向第二多个存储单元提供补偿电压差，其中擦除电压差大于补偿电压差。

5. 发明授权

US6160723A Charge pump circuit including level shifters for threshold voltage cancellation and clock signal boosting, and memory device using same 有权
标题翻译：电荷泵电路包括用于阈值电压消除和时钟信号提升的电平转换器，以及使用它的存储器件
公开(公告)号：US6160723A
公开(公告)日：2000-12-12
申请号：US259234
申请日：1999-03-01
申请人： Tz-yi Liu
发明人： Tz-yi Liu
IPC分类号： H02M3/07 , H02M3/18
CPC分类号： H02M3/073
摘要： A charge pump circuit includes feedback level shifters for providing threshold voltage cancellation and feedforward level shifters for providing boosted clocking signals to generate a high pumped output voltage from a low supply voltage. The charge pump circuit includes plurality of switching circuits each including first and second signal terminals and a control terminal adapted to receive a control signal. Each switching circuit couples its first signal terminal to its second signal terminal responsive to the control signal. The signal terminals of the plurality of switching circuits are connected in series between an input voltage node and an output voltage node. A plurality of energy storage circuits each have a first terminal coupled to a respective voltage node formed by the interconnection between adjacent switching circuits and a second terminal adapted to receive a clocking signal. At least one feedback level shifting circuit is coupled between a selected one of the voltage nodes and the control terminal of a switching circuit between the selected voltage node the input node, each feedback level shifting circuit applying the voltage on the voltage node to the control terminal responsive to a clock signal. At least one feedforward level shifting circuit is coupled between a selected one of the voltage nodes and the second terminal of one of the energy storage circuits coupled to a voltage node between the selected voltage node and the output node. Each feedforward level shifting circuit applies the voltage on the voltage node to the second terminal responsive to a clock signal.
摘要翻译：电荷泵电路包括用于提供阈值电压消除的反馈电平移位器和用于提供升压时钟信号以从低电源电压产生高泵浦输出电压的前馈电平移位器。电荷泵电路包括各自包括第一和第二信号端的多个开关电路和适于接收控制信号的控制端。响应于控制信号，每个开关电路将其第一信号端耦合到其第二信号端。多个开关电路的信号端子串联连接在输入电压节点和输出电压节点之间。多个能量存储电路各自具有耦合到由相邻开关电路之间的互连形成的相应电压节点的第一端子和适于接收定时信号的第二端子。至少一个反馈电平移位电路耦合在所选择的一个电压节点和所选择的电压节点之间的开关电路的输入节点之间，每个反馈电平移位电路将电压节点上的电压施加到控制端响应时钟信号。至少一个前馈电平移位电路耦合在所选择的一个电压节点和耦合到所选择的电压节点和输出节点之间的电压节点的能量存储电路中的一个的第二终端。每个前馈电平移位电路响应于时钟信号将电压节点上的电压施加到第二终端。

6. 发明授权

US08699293B2 Non-volatile storage system with dual block programming 有权
标题翻译：具有双块编程的非易失性存储系统
公开(公告)号：US08699293B2
公开(公告)日：2014-04-15
申请号：US13095779
申请日：2011-04-27
申请人： Tianhong Yan , Tz-yi Liu , Roy E. Scheuerlein
发明人： Tianhong Yan , Tz-yi Liu , Roy E. Scheuerlein
IPC分类号： G11C5/02 , G11C5/06 , G11C7/18 , G11C8/14 , G11C8/12
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0023 , G11C13/003 , G11C2213/71 , G11C2213/73 , G11C2213/77
摘要： A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non-volatile storage elements, a plurality of bit lines connected to the blocks of non-volatile storage elements, multiple sets of word lines drivers such that each set of word line drivers is positioned between two adjacent blocks for driving word lines connected to the two adjacent blocks, global data lines, local data lines in selective communication with the bit lines, one or more selection circuits that selectively connect the global data lines to selected local data lines and connect unselected local data lines to one or more unselected bit line signals and control circuitry in communication with the one or more selection circuits and the global data lines. The control circuitry concurrently programs non-volatile storage elements of two adjacent blocks by applying programming signals on word lines connected to the two adjacent blocks and applying programming signals on appropriate bit lines via the global data lines and the one or more selection circuits.
摘要翻译：公开了一种非易失性存储系统，其包括多个非易失性存储元件块，连接到非易失性存储元件的块的多个字线，使得每个字线连接到非易失性存储元件的相邻块存储元件，连接到非易失性存储元件块的多个位线，多组字线驱动器，使得每组字线驱动器位于两个相邻块之间，用于驱动连接到两个相邻块的字线，全局数据线，与位线选择性通信的本地数据线，一个或多个选择电路，其选择性地将全局数据线连接到选定的本地数据线，并将未选择的本地数据线连接到一个或多个未选位线信号和控制电路与一个或多个选择电路和全局数据线的通信。控制电路通过在连接到两个相邻块的字线上应用编程信号并经由全局数据线和一个或多个选择电路在适当的位线上施加编程信号来同时对两个相邻块的非易失性存储元件进行编程。

7. 发明授权

US08213243B2 Program cycle skip 有权
标题翻译：程序循环跳过
公开(公告)号：US08213243B2
公开(公告)日：2012-07-03
申请号：US12638729
申请日：2009-12-15
申请人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
发明人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0007 , G11C13/0061 , G11C17/165 , G11C17/18 , G11C2013/0076 , G11C2013/0085 , G11C2213/71
摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.
摘要翻译：非易失性存储系统包括在编程页面（或其他单元）数据时跳过编程周期的技术。在对页面（或其他单元）数据的当前子集进行编程时，系统将评估页面（或其他单元）的下一个子集是否应编程为非易失性存储元素或跳过。不应被跳过的页面（或其他单元）的子集被编程到非易失性存储元件中。一些实施例包括将适当数据传送到临时锁存器/寄存器，以准备编程，同时评估是编程还是跳过编程。

8. 发明申请

US20120154022A1 Charge Pump System that Dynamically Selects Number of Active Stages 有权
标题翻译：动力选择活动阶段的电荷泵系统
公开(公告)号：US20120154022A1
公开(公告)日：2012-06-21
申请号：US12973493
申请日：2010-12-20
申请人： Marco Cazzaniga , Tz-Yi Liu
发明人： Marco Cazzaniga , Tz-Yi Liu
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , G11C5/145 , G11C29/021 , H02M2001/008 , H02M2003/077
摘要： A multi-stage charge pump selects the number of active stages dynamically. In the exemplary embodiment, this is done by having a multi-stage master charge pump section in which the number of active stages is settable and a slave charge pump section that is of the same design as the master section. The master section is used drive the external load, while the slave section drives an adjustable internal load. The adjustable load is set by control logic by comparing the operation of the two sections. The control logic then operates the slave sections with a different number of active stages than the master stage in order to determine whether the master stage is using the optimal number of active stages. The control logic can then change the number of active stages accordingly.
摘要翻译：多级电荷泵动态选择有效级数。在该示例性实施例中，这通过具有其中活动级数可设置的多级主电荷泵部分和与主部分具有相同设计的从电荷泵部分来完成。主部分用于驱动外部负载，而从部分驱动可调内部负载。可调负载由控制逻辑通过比较两部分的操作来设定。然后，控制逻辑以与主级不同的有效级数操作从部件，以便确定主级是使用最佳数量的有效级。然后，控制逻辑可以相应地改变活动阶段的数量。

9. 发明授权

US07366027B2 Method and apparatus for erasing memory 有权
标题翻译：擦除存储器的方法和装置
公开(公告)号：US07366027B2
公开(公告)日：2008-04-29
申请号：US11003502
申请日：2004-12-03
申请人： Vinod Lakhani , Tz-Yi Liu
发明人： Vinod Lakhani , Tz-Yi Liu
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： The present invention provides a method and apparatus for erasing memory blocks. The apparatus includes a first plurality of memory cells formed in a substrate and a second plurality of memory cells formed in the substrate. The apparatus further includes a bias circuit adapted to provide an erasing voltage differential to the first plurality of memory cells and a compensating voltage differential to the second plurality of memory cells, wherein the erasing voltage differential is larger than the compensating voltage differential.
摘要翻译：本发明提供一种擦除存储块的方法和装置。该装置包括形成在基板中的第一多个存储单元和形成在基板中的第二多个存储单元。该装置还包括偏置电路，其适于向第一多个存储单元提供擦除电压差，以及向第二多个存储单元提供补偿电压差，其中擦除电压差大于补偿电压差。

10. 发明授权

US08427890B2 Program cycle skip 有权
标题翻译：程序循环跳过
公开(公告)号：US08427890B2
公开(公告)日：2013-04-23
申请号：US13488609
申请日：2012-06-05
申请人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
发明人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0007 , G11C13/0061 , G11C17/165 , G11C17/18 , G11C2013/0076 , G11C2013/0085 , G11C2213/71
摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.
摘要翻译：非易失性存储系统包括在编程页面（或其他单元）数据时跳过编程周期的技术。在对页面（或其他单元）数据的当前子集进行编程时，系统将评估页面（或其他单元）的下一个子集是否应编程为非易失性存储元素或跳过。不应被跳过的页面（或其他单元）的子集被编程到非易失性存储元件中。一些实施例包括将适当数据传送到临时锁存器/寄存器，以准备编程，同时评估是编程还是跳过编程。

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