专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07870513B2 Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
标题翻译：专用集成电路等效的可编程逻辑和相关方法
公开(公告)号：US07870513B2
公开(公告)日：2011-01-11
申请号：US11801082
申请日：2007-05-07
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： G06F17/50 , H03K19/173 , H03K19/177
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分（“LE”）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

2. 发明授权

US07733121B2 Methods and apparatus for programmably powering down structured application-specific integrated circuits 失效
标题翻译：用于可编程断电结构化应用专用集成电路的方法和装置
公开(公告)号：US07733121B2
公开(公告)日：2010-06-08
申请号：US11999269
申请日：2007-12-03
申请人： Hee Kong Phoon , Kar Keng Chua
发明人： Hee Kong Phoon , Kar Keng Chua
IPC分类号： H03K19/173
CPC分类号： H03K19/1735
摘要： Methods and apparatus for programmably powering down a structured application-specific integrated circuit are provided. At least one of the programmable layers of the structured ASIC that frequently provides some programmability as between or among a small number of alternative functions is used to provide this programmability.
摘要翻译：提供了可编程断电结构化应用专用集成电路的方法和装置。结构化ASIC的可编程层中的至少一个经常提供一些可编程性之间或之间的少量替代功能被提供这种可编程性。

3. 发明授权

US07304497B2 Methods and apparatus for programmably powering down structured application-specific integrated circuits 有权
标题翻译：用于可编程断电结构化应用专用集成电路的方法和装置
公开(公告)号：US07304497B2
公开(公告)日：2007-12-04
申请号：US11119312
申请日：2005-04-29
申请人： Hee Kong Phoon , Kar Keng Chua
发明人： Hee Kong Phoon , Kar Keng Chua
IPC分类号： G06F7/38 , H03K19/173 , H01L25/00 , H01L29/00
CPC分类号： H03K19/1735
摘要： Methods and apparatus for programmably powering down a structured application-specific integrated circuit are provided. At least one of the programmable layers of the structured ASIC that frequently provides some programmability as between or among a small number of alternative functions is used to provide this programmability.
摘要翻译：提供了可编程断电结构化应用专用集成电路的方法和装置。结构化ASIC的可编程层中的至少一个经常提供一些可编程性之间或之间的少量替代功能被提供这种可编程性。

4. 发明授权

US07304496B2 Mask-programmable logic device with programmable input/output ports 有权
标题翻译：具有可编程输入/输出端口的面罩可编程逻辑器件
公开(公告)号：US07304496B2
公开(公告)日：2007-12-04
申请号：US11117588
申请日：2005-04-28
申请人： Hee Kong Phoon , Kian Chin Yap
发明人： Hee Kong Phoon , Kian Chin Yap
IPC分类号： H03K19/173 , H03K19/00
CPC分类号： H03K19/17748 , H03K19/17744 , H03K19/17796
摘要： A mask-programmable logic device includes a macrocell having an external input/output port for “place-and-route” programming by addition of metallization layers. A programmable “fixed” layer allows the external input/output port to be isolated from the remainder of the macrocell so that it “floats,” allowing signals to be routed through the external input/output port when the macrocell is not in use, to reduce routing blockages. The macrocell also may have at least one internal input/output port, potentially connected to different logic circuits, and a programmable “fixed” layer that can be used to control which internal input/output port is connected to the external input/output port. By thus allowing multiple logic circuits to share a single external input/output port, routing blockages are reduced.
摘要翻译：掩模可编程逻辑器件包括具有用于通过添加金属化层进行“放置和路由”编程的外部输入/输出端口的宏单元。可编程“固定”层允许外部输入/输出端口与宏单元的其余部分隔离，使其“浮动”，当宏单元未被使用时允许信号通过外部输入/输出端口路由到减少路由阻塞。宏单元还可以具有至少一个可能连接到不同逻辑电路的内部输入/输出端口以及可用于控制哪个内部输入/输出端口连接到外部输入/输出端口的可编程“固定”层。通过这样允许多个逻辑电路共享单个外部输入/输出端口，减少了路由阻塞。

5. 发明申请

US20130002295A1 APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS 有权
标题翻译：可编程逻辑及相关方法的应用特定集成电路等效
公开(公告)号：US20130002295A1
公开(公告)日：2013-01-03
申请号：US13614819
申请日：2012-09-13
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： H03K19/173
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（HLE）的ASIC架构，提供FPGA等效FPGA以提供更高效和经济性，每个ASIC架构可以提供FPGA逻辑元件（LE）的全部功能的一部分）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

6. 发明申请

US20110084727A1 APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS 有权
标题翻译：可编程逻辑及相关方法的应用特定集成电路等效
公开(公告)号：US20110084727A1
公开(公告)日：2011-04-14
申请号：US12967851
申请日：2010-12-14
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分（“LE”）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

7. 发明授权

US08291355B2 Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
标题翻译：专用集成电路等效的可编程逻辑和相关方法
公开(公告)号：US08291355B2
公开(公告)日：2012-10-16
申请号：US12967851
申请日：2010-12-14
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： G06F17/50
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（HLE）的ASIC架构，提供FPGA等效FPGA以提供更高效和经济性，每个ASIC架构可以提供FPGA逻辑元件（LE）的全部功能的一部分）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

8. 发明授权

US07305640B1 Programmable soft macro memory using gate array base cells 有权
标题翻译：使用门阵列基本单元的可编程软宏存储器
公开(公告)号：US07305640B1
公开(公告)日：2007-12-04
申请号：US10987986
申请日：2004-11-12
申请人： Hee Kong Phoon , Boon Jin Ang , Wei Yee Koay , Bee Yee Ng
发明人： Hee Kong Phoon , Boon Jin Ang , Wei Yee Koay , Bee Yee Ng
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A system generates memory unit designs tailored to requirements. The system receives a set of specifications for one or more memory units. The set of specifications includes the memory type, the number of memory access ports, and the data width. The system assembles a memory unit schematic from a library of schematic modules defining memory unit components, including memory cells, address decoders, registers, drivers, sense amplifiers, and optionally self-testing components. The system creates a layout for the memory unit from a library of layout modules corresponding to the library of schematic modules. The library of layout modules includes memory unit floorplans specifying the location of layout modules within a memory unit. The system selects from different memory unit floorplans to create an optimized memory unit layout. The memory unit schematic can be validated using functional testing methods. The system processes the memory unit layout to produce a device configuration.
摘要翻译：系统生成适合要求的内存单元设计。系统接收一组或多个存储单元的规格。该组规范包括内存类型，内存访问端口数量和数据宽度。该系统从定义存储器单元组件的原理图模块库中组装存储器单元原理图，包括存储器单元，地址解码器，寄存器，驱动器，读出放大器以及可选择的自检部件。系统从与原理图模块库相对应的布局模块库创建存储单元的布局。布局模块库包括指定布局模块在存储器单元内的位置的存储单元平面图。系统从不同的存储单元平面图中选择以创建优化的存储器单元布局。存储单元原理图可以使用功能测试方法进行验证。系统处理存储器单元布局以产生器件配置。

9. 发明申请

US20190326210A1 Fabric Die to Fabric Die Interconnect for Modularized Integrated Circuit Devices 审中-公开
公开(公告)号：US20190326210A1
公开(公告)日：2019-10-24
申请号：US16456647
申请日：2019-06-28
申请人： Chee Hak Teh , Chee Seng Leong , Lai Guan Tang , Han Wooi Lim , Hee Kong Phoon
发明人： Chee Hak Teh , Chee Seng Leong , Lai Guan Tang , Han Wooi Lim , Hee Kong Phoon
IPC分类号： H01L23/528 , H01L23/498 , H03K19/177
摘要： The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.

10. 发明授权

US08504963B2 Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
标题翻译：专用集成电路等效的可编程逻辑和相关方法
公开(公告)号：US08504963B2
公开(公告)日：2013-08-06
申请号：US13614819
申请日：2012-09-13
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： G06F17/50
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分（“LE”）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式