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1. 发明授权

US07870513B2 Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
标题翻译：专用集成电路等效的可编程逻辑和相关方法
公开(公告)号：US07870513B2
公开(公告)日：2011-01-11
申请号：US11801082
申请日：2007-05-07
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： G06F17/50 , H03K19/173 , H03K19/177
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分（“LE”）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

2. 发明授权

US07733121B2 Methods and apparatus for programmably powering down structured application-specific integrated circuits 失效
标题翻译：用于可编程断电结构化应用专用集成电路的方法和装置
公开(公告)号：US07733121B2
公开(公告)日：2010-06-08
申请号：US11999269
申请日：2007-12-03
申请人： Hee Kong Phoon , Kar Keng Chua
发明人： Hee Kong Phoon , Kar Keng Chua
IPC分类号： H03K19/173
CPC分类号： H03K19/1735
摘要： Methods and apparatus for programmably powering down a structured application-specific integrated circuit are provided. At least one of the programmable layers of the structured ASIC that frequently provides some programmability as between or among a small number of alternative functions is used to provide this programmability.
摘要翻译：提供了可编程断电结构化应用专用集成电路的方法和装置。结构化ASIC的可编程层中的至少一个经常提供一些可编程性之间或之间的少量替代功能被提供这种可编程性。

3. 发明授权

US07304497B2 Methods and apparatus for programmably powering down structured application-specific integrated circuits 有权
标题翻译：用于可编程断电结构化应用专用集成电路的方法和装置
公开(公告)号：US07304497B2
公开(公告)日：2007-12-04
申请号：US11119312
申请日：2005-04-29
申请人： Hee Kong Phoon , Kar Keng Chua
发明人： Hee Kong Phoon , Kar Keng Chua
IPC分类号： G06F7/38 , H03K19/173 , H01L25/00 , H01L29/00
CPC分类号： H03K19/1735
摘要： Methods and apparatus for programmably powering down a structured application-specific integrated circuit are provided. At least one of the programmable layers of the structured ASIC that frequently provides some programmability as between or among a small number of alternative functions is used to provide this programmability.
摘要翻译：提供了可编程断电结构化应用专用集成电路的方法和装置。结构化ASIC的可编程层中的至少一个经常提供一些可编程性之间或之间的少量替代功能被提供这种可编程性。

4. 发明授权

US08291355B2 Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
标题翻译：专用集成电路等效的可编程逻辑和相关方法
公开(公告)号：US08291355B2
公开(公告)日：2012-10-16
申请号：US12967851
申请日：2010-12-14
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： G06F17/50
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（HLE）的ASIC架构，提供FPGA等效FPGA以提供更高效和经济性，每个ASIC架构可以提供FPGA逻辑元件（LE）的全部功能的一部分）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

5. 发明申请

US20130002295A1 APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS 有权
标题翻译：可编程逻辑及相关方法的应用特定集成电路等效
公开(公告)号：US20130002295A1
公开(公告)日：2013-01-03
申请号：US13614819
申请日：2012-09-13
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： H03K19/173
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（HLE）的ASIC架构，提供FPGA等效FPGA以提供更高效和经济性，每个ASIC架构可以提供FPGA逻辑元件（LE）的全部功能的一部分）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

6. 发明申请

US20110084727A1 APPLICATION-SPECIFIC INTEGRATED CIRCUIT EQUIVALENTS OF PROGRAMMABLE LOGIC AND ASSOCIATED METHODS 有权
标题翻译：可编程逻辑及相关方法的应用特定集成电路等效
公开(公告)号：US20110084727A1
公开(公告)日：2011-04-14
申请号：US12967851
申请日：2010-12-14
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分（“LE”）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

7. 发明授权

US08504963B2 Application-specific integrated circuit equivalents of programmable logic and associated methods 有权
标题翻译：专用集成电路等效的可编程逻辑和相关方法
公开(公告)号：US08504963B2
公开(公告)日：2013-08-06
申请号：US13614819
申请日：2012-09-13
申请人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
发明人： Kar Keng Chua , Sammy Cheung , Hee Kong Phoon , Kim Pin Tan , Wei Lian Goay
IPC分类号： G06F17/50
CPC分类号： H03K19/177 , H03K19/1737
摘要： Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
摘要翻译：通过使用包括多个所谓的混合逻辑元件（“HLE”）的ASIC架构，提供了ASIC等效的FPGA，使其更加高效和经济，每个ASIC架构可以提供FPGA逻辑元件的全部功能的一部分（“LE”）。实现用户逻辑设计的每个FPGA LE的功能可以被映射到一个或多个HLE而不重新合成用户的逻辑。只有使用必要的HLE才能执行每个LE的功能。每个LE和（1）一个HLE或（2）一组HLE之间的一对一等价有助于在FPGA和ASIC设计之间的任一方向上的映射（无需重新合成）。

8. 发明授权

US08694944B1 Predicting routability of integrated circuits 有权
标题翻译：预测集成电路的可布线性
公开(公告)号：US08694944B1
公开(公告)日：2014-04-08
申请号：US12643528
申请日：2009-12-21
申请人： Sze Huey Soo , Thow Pang Chong , Boon Jin Ang , Kar Keng Chua
发明人： Sze Huey Soo , Thow Pang Chong , Boon Jin Ang , Kar Keng Chua
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/504 , G06F17/5054
摘要： Methods, computer program products, and systems are disclosed associated with calculating a routability metric for a second IC design using inputs from the compilation to a first IC design. The first and second IC designs are alternative implementation options for a user circuit design, such as FPGA and structured ASIC options. Information about user design demands on routing resources of one IC design are considered along with information about the projected supply of routing resources in another IC design, to produce a routing metric. The routing metric may be mapped to a degree of difficulty indicator, and either may be used to condition a compile of the user circuit to the second IC design or be used in other ways.
摘要翻译：公开了使用从汇编到第一IC设计的输入来计算第二IC设计的可路由度量的方法，计算机程序产品和系统。第一和第二IC设计是用户电路设计的替代实现选项，例如FPGA和结构化ASIC选项。关于一个IC设计的路由资源的用户设计需求的信息以及关于在另一个IC设计中的路由资源的预计供应的信息，以产生路由度量。路由度量可以映射到难度指标，并且可以用于将用户电路的编译调节到第二IC设计或以其他方式使用。

9. 发明授权

US08533250B1 Multiplier with built-in accumulator 有权
标题翻译：带内置蓄能器的乘数
公开(公告)号：US08533250B1
公开(公告)日：2013-09-10
申请号：US12486231
申请日：2009-06-17
申请人： Kok Yoong Foo , Yan Jiong Boo , Geok Sun Chong , Boon Jin Ang , Kar Keng Chua
发明人： Kok Yoong Foo , Yan Jiong Boo , Geok Sun Chong , Boon Jin Ang , Kar Keng Chua
IPC分类号： G06F7/38 , G06F7/00
CPC分类号： G06F7/5443
摘要： Circuits for a multiplier with a built-in accumulator and a method of performing multiplication with accumulation are disclosed. An embodiment of the disclosed circuits includes a logic circuit coupled to receive two inputs. The logic circuit is capable of generating a plurality of value bits from the inputs received. In one embodiment, the logic circuit includes a Booth recoder circuit that generates a plurality of partial products. A block of adders is coupled to logic circuit to receive and sum up the value bits. An adder adds the summation result from the block of adders to a previous accumulated value to generate intermediate sum and carry values. An accumulator, coupled to the adder, receives and stores the intermediate values.
摘要翻译：公开了具有内置累加器的乘法器的电路和执行与累加相乘的方法。所公开的电路的实施例包括耦合以接收两个输入的逻辑电路。逻辑电路能够从接收到的输入产生多个值比特。在一个实施例中，逻辑电路包括生成多个部分乘积的布斯重新编码器电路。一组加法器耦合到逻辑电路以接收和总结值位。加法器将来自加法器块的求和结果相加到先前的累积值，以产生中间和和携带值。耦合到加法器的累加器接收并存储中间值。

10. 发明授权

US08327199B1 Integrated circuit with configurable test pins 有权
标题翻译：具有可配置测试引脚的集成电路
公开(公告)号：US08327199B1
公开(公告)日：2012-12-04
申请号：US12718914
申请日：2010-03-05
申请人： Jayabrata Ghosh Dastidar , Chiew Khiang Kuit , Siew Ling Yeoh , Jun Pin Tan , Kok Sun Chia , Yee Liang Tan , Kar Keng Chua
发明人： Jayabrata Ghosh Dastidar , Chiew Khiang Kuit , Siew Ling Yeoh , Jun Pin Tan , Kok Sun Chia , Yee Liang Tan , Kar Keng Chua
IPC分类号： G01R31/28
CPC分类号： G01R31/3172 , G01R31/318516
摘要： Integrated circuits (ICs) with configurable test pins and a method of testing an IC are disclosed. An IC has input/output (I/O) pins that can be configured either as a test input pin, a test output pin or a user I/O pin. Selector circuits are used to selectively route and couple the I/O pins to various logic blocks and test circuitry on the IC. Selector circuits are also used to selectively couple either a user output or a test output to different I/O pins on the IC. Switches are used to configure the selector circuits and route test signals within the IC. Different configurations of the switches determine how the signals are routed. Test input signals from an I/O pin may be routed to any test circuitry within the IC and test output signals from a test circuit may be routed to any I/O pin on the IC.
摘要翻译：公开了具有可配置测试引脚的集成电路（IC）和测试IC的方法。 IC具有可配置为测试输入引脚，测试输出引脚或用户I / O引脚的输入/输出（I / O）引脚。选择器电路用于选择性地将I / O引脚路由和耦合到IC上的各种逻辑块和测试电路。选择器电路还用于选择性地将用户输出或测试输出耦合到IC上的不同I / O引脚。开关用于配置选择器电路并在IC内部路由测试信号。交换机的不同配置决定信号的路由。来自I / O引脚的测试输入信号可以被路由到IC内的任何测试电路，并且来自测试电路的测试输出信号可以被路由到IC上的任何I / O引脚。

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