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1. 发明申请

US20100095090A1 BARRIER SYNCHRONIZATION METHOD, DEVICE, AND MULTI-CORE PROCESSOR 有权
标题翻译： BARRIER同步方法，设备和多核处理器
公开(公告)号：US20100095090A1
公开(公告)日：2010-04-15
申请号：US12638746
申请日：2009-12-15
申请人： Hideyuki UNNO , Masaki Ukai , Matthew Depetro
发明人： Hideyuki UNNO , Masaki Ukai , Matthew Depetro
IPC分类号： G06F15/76 , G06F9/02 , G06F12/08
CPC分类号： G06F9/52 , G06F9/522
摘要： A barrier synchronization device for realizing barrier synchronization of at least 2 processor cores belonging to a same synchronization group among a plurality of processor cores is included in a multi-core processor having a plurality of processor cores, and when two or more processor cores in that multi-core processor belong to the same synchronization group, the included barrier synchronization device is used for realizing barrier synchronization.
摘要翻译：用于实现多个处理器核心中属于同一同步组的至少2个处理器核心的屏障同步的屏障同步装置包括在具有多个处理器核心的多核处理器中，并且当该处理器核心中的两个或多个处理器核心多核处理器属于同一同步组，所包含的屏障同步装置用于实现屏障同步。

2. 发明授权

US07971029B2 Barrier synchronization method, device, and multi-core processor 有权
标题翻译：屏障同步方法，设备和多核处理器
公开(公告)号：US07971029B2
公开(公告)日：2011-06-28
申请号：US12638746
申请日：2009-12-15
申请人： Hideyuki Unno , Masaki Ukai , Matthew Depetro
发明人： Hideyuki Unno , Masaki Ukai , Matthew Depetro
IPC分类号： G06F15/177 , G06F15/76
CPC分类号： G06F9/52 , G06F9/522
摘要： A barrier synchronization device for realizing barrier synchronization of at least 2 processor cores belonging to a same synchronization group among a plurality of processor cores is included in a multi-core processor having a plurality of processor cores, and when two or more processor cores in that multi-core processor belong to the same synchronization group, the included barrier synchronization device is used for realizing barrier synchronization.
摘要翻译：用于实现多个处理器核心中属于同一同步组的至少2个处理器核心的屏障同步的屏障同步装置包括在具有多个处理器核心的多核处理器中，并且当该处理器核心中的两个或多个处理器核心多核处理器属于同一同步组，所包含的屏障同步装置用于实现屏障同步。

3. 发明申请

US20080320360A1 CONTROL METHOD OF INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING DEVICE 失效
标题翻译：信息处理设备和信息处理设备的控制方法
公开(公告)号：US20080320360A1
公开(公告)日：2008-12-25
申请号：US12198577
申请日：2008-08-26
申请人： Hideyuki UNNO , Masaki Ukai , Naozumi Aoki
发明人： Hideyuki UNNO , Masaki Ukai , Naozumi Aoki
IPC分类号： G06F11/10
CPC分类号： H04L1/0042 , G06F11/349 , H04L1/0047 , H04L25/4915
摘要： A transmitting side device (10) and a receiving side device (20) are connected to each other via a bus (30) comprising TAG bits (31), data bits (32) and error detection/correction ECC bits (33). The transmitting side device (10) uses a redundant bit inversion circuit (14) to invert different bits of the ECC bits (33) corresponding to trigger signals (41 & 42). In the receiving side device (20), a determination circuit (24), which has received an error report signal (26) from an error detection/correction circuit (22), determines, from the position of an error bit in the ECC bits (33), which one of the trigger signals (41 & 42) has been transmitted from the transmitting side device (10).
摘要翻译：发送侧设备（10）和接收侧设备（20）经由包括TAG位（31），数据位（32）和错误检测/校正ECC位（33）的总线（30）彼此连接。发送侧装置（10）使用冗余比特反相电路（14）反相对应于触发信号（41和42）的ECC比特（33）的不同比特。在接收侧设备（20）中，从错误检测/校正电路（22）接收到错误报告信号（26）的确定电路（24）从ECC位中的错误位的位置确定（33），所述触发信号（41和42）中的哪一个已经从所述发送侧装置（10）发送。

4. 发明申请

US20110185128A1 Memory access method and information processing apparatus 审中-公开
标题翻译：存储器访问方法和信息处理装置
公开(公告)号：US20110185128A1
公开(公告)日：2011-07-28
申请号：US13064568
申请日：2011-03-31
申请人： Masaki Ukai , Hideyuki Unno , Megumi Yokoi
发明人： Masaki Ukai , Hideyuki Unno , Megumi Yokoi
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/082 , G06F12/0822 , G06F12/0831 , G06F2212/1024 , G06F2212/1048 , G06F2212/2542
摘要： To maintain data consistency in an information processing apparatus in which a nodes are coupled, takeout information indicating that data of the node is taken out to a secondary memory of another node is stored in a directory of each node. When a cache miss occurs during a memory access to a secondary memory of one node, the one node judges whether a destination of the memory access is a main or the secondary memory thereof. If the memory access is destination is the main or secondary memory of the one node, the directory is indexed and retrieved to judge whether a directory hit occurs, and if no directory hit occurs, a memory access is performed by the one node based on the memory access.
摘要翻译：为了在其中节点被耦合的信息处理设备中保持数据一致性，将指示节点的数据取出到另一个节点的辅助存储器的取出信息存储在每个节点的目录中。当在对一个节点的辅助存储器的存储器访问期间发生高速缓存未命中时，一个节点判断存储器访问的目的地是主存储器还是其二次存储器。如果存储器访问是目的地是一个节点的主存储器或辅助存储器，则对目录进行索引和检索，以判断是否发生目录命中，并且如果没有发生目录命中，则基于一个节点执行存储器访问内存访问。

5. 发明授权

US08301969B2 Control method of information processing device and information processing device 失效
标题翻译：信息处理装置和信息处理装置的控制方法
公开(公告)号：US08301969B2
公开(公告)日：2012-10-30
申请号：US12198577
申请日：2008-08-26
申请人： Hideyuki Unno , Masaki Ukai , Naozumi Aoki
发明人： Hideyuki Unno , Masaki Ukai , Naozumi Aoki
IPC分类号： H03M13/00
CPC分类号： H04L1/0042 , G06F11/349 , H04L1/0047 , H04L25/4915
摘要： A transmitting side device (10) and a receiving side device (20) are connected to each other via a bus (30) comprising TAG bits (31), data bits (32) and error detection/correction ECC bits (33). The transmitting side device (10) uses a redundant bit inversion circuit (14) to invert different bits of the ECC bits (33) corresponding to trigger signals (41 & 42). In the receiving side device (20), a determination circuit (24), which has received an error report signal (26) from an error detection/correction circuit (22), determines, from the position of an error bit in the ECC bits (33), which one of the trigger signals (41 & 42) has been transmitted from the transmitting side device (10).
摘要翻译：发送侧设备（10）和接收侧设备（20）经由包括TAG位（31），数据位（32）和错误检测/校正ECC位（33）的总线（30）彼此连接。发送侧装置（10）使用冗余比特反相电路（14）反相对应于触发信号（41和42）的ECC比特（33）的不同比特。在接收侧设备（20）中，从错误检测/校正电路（22）接收到错误报告信号（26）的确定电路（24）从ECC位中的错误位的位置确定（33），所述触发信号（41和42）中的哪一个已经从所述发送侧装置（10）发送。

6. 发明申请

US20080320201A1 CENTRAL PROCESSING APPARATUS, CONTROL METHOD THEREFOR AND INFORMATION PROCESSING SYSTEM 有权
标题翻译：中央处理设备及其控制方法及信息处理系统
公开(公告)号：US20080320201A1
公开(公告)日：2008-12-25
申请号：US12199004
申请日：2008-08-27
申请人： Hideyuki UNNO , Masaki Ukai
发明人： Hideyuki UNNO , Masaki Ukai
IPC分类号： G06F13/28
CPC分类号： G06F12/0607 , G06F13/1647
摘要： A plurality of system controllers 300 each comprising a memory medium 400 and an I/O device 500 under the control of the system controller 300 are connected to a CPU node 100 by way of a plurality of system buses 200. The CPU node 100 executes a memory interleave for distributing memory accesses to the system buses 200 (i.e., the system controllers 300). In performing an I/O access to the I/O device 500, the CPU node 100 firstly inquires from a representative system controller 300 (SC0) as to which system bus 200 (i.e., a system controller 300) has a target I/O device 500 and then executes an actual I/O access to the system bus 200 returned in a response from the SC0. Even when the CPU node 100 executes a memory interleave in the case of a memory-mapped I/O, the CPU node 100 is not required to manage the location information of the I/O device 500.
摘要翻译：在系统控制器300的控制下，包括存储介质400和I / O设备500的多个系统控制器300通过多个系统总线200连接到CPU节点100.CPU节点100执行用于分配对系统总线200（即，系统控制器300）的存储器访问的存储器交错。在执行对I / O设备500的I / O访问时，CPU节点100首先向代表系统控制器300（SC0）询问哪个系统总线200（即，系统控制器300）具有目标I / O 然后对来自SC0的响应中返回的系统总线200执行实际的I / O访问。即使当CPU节点100在存储器映射的I / O的情况下执行存储器交错时，CPU节点100也不需要管理I / O设备500的位置信息。

7. 发明授权

US08015326B2 Central processing apparatus, control method therefor and information processing system 有权
标题翻译：中央处理装置及其控制方法及信息处理系统
公开(公告)号：US08015326B2
公开(公告)日：2011-09-06
申请号：US12199004
申请日：2008-08-27
申请人： Hideyuki Unno , Masaki Ukai
发明人： Hideyuki Unno , Masaki Ukai
IPC分类号： G06F3/00
CPC分类号： G06F12/0607 , G06F13/1647
摘要： A plurality of system controllers 300 each comprising a memory medium 400 and an I/O device 500 under the control of the system controller 300 are connected to a CPU node 100 by way of a plurality of system buses 200. The CPU node 100 executes a memory interleave for distributing memory accesses to the system buses 200 (i.e., the system controllers 300). In performing an I/O access to the I/O device 500, the CPU node 100 firstly inquires from a representative system controller 300 (SC0) as to which system bus 200 (i.e., a system controller 300) has a target I/O device 500 and then executes an actual I/O access to the system bus 200 returned in a response from the SC0. Even when the CPU node 100 executes a memory interleave in the case of a memory-mapped I/O, the CPU node 100 is not required to manage the location information of the I/O device 500.
摘要翻译：在系统控制器300的控制下，包括存储介质400和I / O设备500的多个系统控制器300通过多个系统总线200连接到CPU节点100.CPU节点100执行用于分配对系统总线200（即，系统控制器300）的存储器访问的存储器交错。在执行对I / O设备500的I / O访问时，CPU节点100首先向代表系统控制器300（SC0）询问哪个系统总线200（即，系统控制器300）具有目标I / O 然后对来自SC0的响应中返回的系统总线200执行实际的I / O访问。即使当CPU节点100在存储器映射的I / O的情况下执行存储器交错时，CPU节点100也不需要管理I / O设备500的位置信息。

8. 发明申请

US20070050505A1 Apparatus and method for data transfer control 审中-公开
标题翻译：数据传输控制的装置和方法
公开(公告)号：US20070050505A1
公开(公告)日：2007-03-01
申请号：US11333327
申请日：2006-01-18
申请人： Hideyuki Unno , Masaki Ukai , Naozumi Aoki
发明人： Hideyuki Unno , Masaki Ukai , Naozumi Aoki
IPC分类号： G06F15/173
CPC分类号： G06F13/404 , H04L49/3018 , H04L49/3027 , H04L49/35 , H04L49/503
摘要： An apparatus for controlling data transfer performed with a computer connected to a data bus, which performs data transfer in one direction, the apparatus includes a data transfer controlling unit that controls the data transfer with the computer by setting a data bandwidth of an input bus to be greater than a data bandwidth of an output bus, where the input bus transfers data to be input to the computer, and the output bus transfers data output by the computer.
摘要翻译：一种用于控制数据传送的装置，该计算机连接到在一个方向上执行数据传输的数据总线，所述装置包括数据传送控制单元，其通过将输入总线的数据带宽设置为大于输出总线的数据带宽，其中输入总线传送要输入到计算机的数据，并且输出总线传送计算机输出的数据。

9. 发明授权

US08370585B2 Data processing system and cache control method 有权
标题翻译：数据处理系统和缓存控制方法
公开(公告)号：US08370585B2
公开(公告)日：2013-02-05
申请号：US12633112
申请日：2009-12-08
申请人： Masaki Ukai
发明人： Masaki Ukai
IPC分类号： G06F12/02
CPC分类号： G06F12/084 , G06F12/0815 , G06F12/0886
摘要： A data processing system is provided. The data processing system includes a plurality of processors, a cache memory shared by the plurality of processors, in which memory a cache line is divided into a plurality of partial writable regions. The plurality of processors are given exclusive access rights to the partial writable region waits.
摘要翻译：提供了一种数据处理系统。数据处理系统包括多个处理器，由多个处理器共享的高速缓冲存储器，其中存储器将高速缓存线划分成多个部分可写入区域。多个处理器被赋予部分可写区域等待的独占访问权限。

10. 发明授权

US07743215B2 Cache-memory control apparatus, cache-memory control method and computer product 有权
标题翻译：缓存存储器控制装置，缓存存储器控制方法和计算机产品
公开(公告)号：US07743215B2
公开(公告)日：2010-06-22
申请号：US11980386
申请日：2007-10-31
申请人： Tomoyuki Okawa , Hiroyuki Kojima , Hideki Sakata , Masaki Ukai
发明人： Tomoyuki Okawa , Hiroyuki Kojima , Hideki Sakata , Masaki Ukai
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0811
摘要： A cache-memory control apparatus controls a level-1 (L1) cache and a level-2 (L2) cache having a cache line divided into a plurality of sub-lines for storing data from the L1 cache. The cache-memory control apparatus includes a control-flag adding unit, an L1 cache control unit, and an L2 cache control unit. The control-flag adding unit provides an SP flag to each of the sub-lines. The L1-cache control unit acquires an access virtual address, and, when there is no data at the access virtual address, outputs an L2 cache-access address to the L2-cache control unit. The L2-cache control unit switches the SP flag based on a virtual page number in an L1 index and a physical page number in an L2 index. Based on the SP flag, corresponding one of the sub-lines is written back to the L1 cache.
摘要翻译：高速缓冲存储器控制装置控制一级（L1）高速缓存和二级（L2）高速缓存，该缓存具有被划分成用于存储来自L1高速缓存的数据的多条子行的高速缓存行。高速缓冲存储器控制装置包括控制标志添加单元，L1高速缓存控制单元和L2高速缓存控制单元。控制标志添加单元向每个子线提供SP标志。 L1高速缓存控制单元获取访问虚拟地址，并且当在访问虚拟地址处没有数据时，向L2高速缓存控制单元输出L2高速缓存访问地址。 L2缓存控制单元基于L1索引中的虚拟页号和L2索引中的物理页号来切换SP标志。基于SP标志，相应的一条子行被写回到L1高速缓存。

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