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1. 发明申请

US20130088279A1 Power Converter 审中-公开
标题翻译：电源转换器
公开(公告)号：US20130088279A1
公开(公告)日：2013-04-11
申请号：US13638372
申请日：2011-04-01
申请人： Hiroki Shimano , Yasuo Noto , Koichi Yahata , Seiji Funaba , Yoshio Akaishi
发明人： Hiroki Shimano , Yasuo Noto , Koichi Yahata , Seiji Funaba , Yoshio Akaishi
IPC分类号： H03K17/284
CPC分类号： H03K17/284 , H02M1/08 , H03K17/163 , H03K2217/0036
摘要： The present invention provides a power converter including a power semiconductor device, a driver circuit section that outputs a driving signal for driving the power semiconductor device, a buffer circuit section that includes a PNP transistor and an NPN transistor and that outputs a gate voltage for driving the power semiconductor device, a first delay circuit section that receives the driving signal and that generates a first delay signal on the basis of the received driving signal, a first MOSFET that has a drain electrode connected with the output of the buffer circuit section and that is driven on the basis of the first delay signal. A current flows through the buffer circuit section and the first MOSFET on the basis of the received driving signal, the first delay circuit section outputs the first delay signal after the buffer circuit section exits the transient state and turns on, and the gate voltage is applied to the power semiconductor device from the buffer circuit section to turn the power semiconductor device on by the switching operation of the first MOSFET based on the first delay signal.
摘要翻译：本发明提供了一种功率转换器，包括功率半导体器件，输出用于驱动功率半导体器件的驱动信号的驱动器电路部分，包括PNP晶体管和NPN晶体管的缓冲电路部分，并且输出用于驱动的栅极电压所述功率半导体器件，接收所述驱动信号并基于所接收的驱动信号产生第一延迟信号的第一延迟电路部，具有与所述缓冲电路部的输出连接的漏电极的第一MOSFET，以及与所述缓冲电路部的输出连接的第一MOSFET，基于第一延迟信号被驱动。 A电流根据接收到的驱动信号流过缓冲电路部分和第一MOSFET，第一延迟电路部分在缓冲电路部分退出瞬态之后输出第一延迟信号并导通，施加栅极电压从缓冲电路部分到功率半导体器件，通过基于第一延迟信号的第一MOSFET的开关操作使功率半导体器件导通。

2. 发明申请

US20090103353A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20090103353A1
公开(公告)日：2009-04-23
申请号：US12338219
申请日：2008-12-18
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/24 , G11C5/14 , G11C8/08
CPC分类号： G11C7/18 , G11C8/14 , G11C11/4085 , G11C11/4087 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/108 , H01L27/1085 , H01L27/10873 , H01L27/10882
摘要： Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.
摘要翻译：构成存储单元板的导体线的导电线和构成存储单元板电极的导线被形成在包括多个存储单元的存储器件的同一互连层中，每个存储单元均包括用于以电荷形式存储数据的电容器。通过将存储单元的电容器形成为平面电容器配置，由于电容器而导致的步骤被去除。因此，可以通过CMOS工艺形成动态半导体存储器件，并且实现适合于与逻辑合并的动态半导体存储器件。 1位的数据由两个存储单元存储，即使由于平面型电容器而使存储单元的电容值减小，也可以可靠地存储数据。

3. 发明申请

US20080137394A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20080137394A1
公开(公告)日：2008-06-12
申请号：US12000343
申请日：2007-12-12
申请人： Hiroki Shimano , Fukashi Morishita , Kazutami Arimoto
发明人： Hiroki Shimano , Fukashi Morishita , Kazutami Arimoto
IPC分类号： G11C5/06
CPC分类号： G11C8/16 , G11C5/063 , G11C7/12 , G11C7/18 , G11C11/405 , G11C11/4094 , G11C11/4097 , G11C2211/4016 , H01L21/84 , H01L27/0207 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： One memory cell is formed of a first port access transistor, a second port access transistor and a storage transistor coupled commonly to these access transistors. The first port access transistor is coupled to a first electrode of the storage transistor, and the second port access transistor is coupled to a third electrode of the storage transistor. These first and second port access transistors enter a selected state when first and second port word lines are selected, respectively, to couple corresponding second and third electrodes of the corresponding storage transistor to first and second port bit lines, respectively. A dual-port memory cell of which scalability can follow miniaturization in a process can be provided.
摘要翻译：一个存储单元由第一端口存取晶体管，第二端口存取晶体管和与这些存取晶体管共同耦合的存储晶体管形成。第一端口存取晶体管耦合到存储晶体管的第一电极，第二端口存取晶体管耦合到存储晶体管的第三电极。当分别选择第一和第二端口字线时，这些第一和第二端口存取晶体管进入选择状态，以将相应的存储晶体管的相应的第二和第三电极分别耦合到第一和第二端口位线。可以提供一种双端口存储单元，其可扩展性可以在一个过程中跟随小型化。

4. 发明授权

US06925022B2 Refresh-free dynamic semiconductor memory device 失效
标题翻译：无刷新动态半导体存储器件
公开(公告)号：US06925022B2
公开(公告)日：2005-08-02
申请号：US10229035
申请日：2002-08-28
申请人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
发明人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/403 , G11C11/405 , G11C11/406 , G11C11/408 , G11C11/409 , G11C29/02 , G11C29/04 , G11C29/14 , G11C7/20
CPC分类号： G11C29/006 , G11C7/1045 , G11C11/401 , G11C11/406 , G11C11/4087 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C29/83 , G11C2029/1204 , G11C2207/104 , G11C2211/4013 , G11C2211/5641
摘要： In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.
摘要翻译：在数据保持模式下，在正常操作模式下的一位/一个单元方案中的数据存储以双位模式重新排列成数据存储，其中数据以一位/双位单元方式存储。在双电池模式中，两个子字线同时被驱动到选择状态，并且在一对位线上读出存储器单元的存储数据，以执行感测操作。因此，可以增加读出电压以改善用于延长刷新间隔的数据保持特性，导致数据保持模式中的功耗降低。

5. 发明授权

US06898137B2 Semiconductor memory device with high-speed sense amplifier 有权
标题翻译：具有高速读出放大器的半导体存储器件
公开(公告)号：US06898137B2
公开(公告)日：2005-05-24
申请号：US10403009
申请日：2003-04-01
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： H01L27/108 , G11C7/06 , G11C7/12 , G11C7/14 , G11C11/401 , G11C11/4091 , G11C11/4099 , H01L21/8242 , G11C7/02
CPC分类号： G11C11/4099 , G11C7/062 , G11C7/12 , G11C7/14 , G11C11/4091
摘要： In a Vss precharge scheme, dummy cells including a bit line contact, a storage node contact and a third contact connected to a Vccs power supply line are arranged in complementary bit lines. In a waiting state, H level data is written in each dummy cell from the Vccs power supply line. Before row activation is started and a normal word line is selected, a dummy word line is driven to a selected state, and the H level data is read from each dummy cell. Therefore, charge in equal amounts is injected to the complementary bit lines, and a shift from a Vss level to the same potential occurs. A sense amplifier uses the potential as a reference voltage to amplify and detect a potential difference between bit lines.
摘要翻译：在Vss预充电方案中，包括位线触点，存储节点触点和连接到Vcc电源线的第三触点的虚拟单元被布置在互补位线中。在等待状态下，从Vcc电源线将H电平数据写入每个虚拟单元。在行激活开始并且选择正常字线之前，将虚拟字线驱动到所选状态，并且从每个虚拟单元读取H电平数据。因此，等量的电荷被注入到互补位线，并且发生从Vss电平到相同电位的偏移。读出放大器使用该电位作为参考电压来放大和检测位线之间的电位差。

6. 发明申请

US20050041514A1 Low-power consumption semiconductor memory device 失效
标题翻译：低功耗半导体存储器件
公开(公告)号：US20050041514A1
公开(公告)日：2005-02-24
申请号：US10949365
申请日：2004-09-27
申请人： Takeshi Fujino , Kazutami Arimoto , Hiroki Shimano
发明人： Takeshi Fujino , Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/405 , G11C7/12 , G11C11/409 , G11C11/4094 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C5/00
CPC分类号： G11C11/4094 , G11C7/12
摘要： A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.
摘要翻译：存储单元单元包括用于彼此存储互补数据的第一存储元件和第二存储元件。在选择状态下，第一和第二存储元件分别连接到互补位线。在待机状态下，位线被预充电到对应于存储在存储单元单元中的数据的电压（Vcc或GND）。可以实现即使在低电源电压下稳定运行的无刷新，低电流消耗的半导体存储器件。

7. 发明授权

US06744684B2 Semiconductor memory device with simple refresh control 有权
公开(公告)号：US06744684B2
公开(公告)日：2004-06-01
申请号：US09777694
申请日：2001-02-07
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C700
CPC分类号： G11C11/40615 , G11C11/406 , G11C2207/104
摘要： A self refresh timer is set constantly to an operation state to render a refresh request signal FAY active periodically. When contention occurs between the refresh request signal FAY and an externally applied read or write command, a row selection related circuit/command generation related circuit controls a row related control signal so that a refresh operation is carried out after, for example, the read or write operation ends. A submemory array SMA is divided more small than that of the conventional case, and the refresh cycle ends in a shorter period of time. Therefore, a read operation and a refresh operation can be completed within a read cycle time. A DRAM core that can be employed with control as simple as that of an SRAM can be realized.

8. 发明授权

US06590511B2 Retrievable memory capable of outputting a piece of data with respect to a plurality of results of retrieve 失效
公开(公告)号：US06590511B2
公开(公告)日：2003-07-08
申请号：US09775711
申请日：2001-02-05
申请人： Isamu Hayashi , Takeshi Fujino , Hideyuki Noda , Hiroki Shimano
发明人： Isamu Hayashi , Takeshi Fujino , Hideyuki Noda , Hiroki Shimano
IPC分类号： H03M700
CPC分类号： H03M7/3084 , G11C15/00 , G11C15/04
摘要： A retrievable memory is provided with a priority encoder. The priority encoder is constituted by encoder units. Each of the encoder units is constituted by an inverter, N-channel MOS transistors and an AND gate. Upon receipt of a signal of H level from a matching line, the encoder unit outputs a signal of H level to a word line, and also outputs a signal of L level to a matching line active signal line MLA1. Then, the encoder units respectively output signals of L level to the word lines. Consequently, even when a plurality of results of a retrieving process are obtained, it is possible to output single data.

9. 发明授权

US06483139B1 Semiconductor memory device formed on semiconductor substrate 有权
标题翻译：形成在半导体衬底上的半导体存储器件
公开(公告)号：US06483139B1
公开(公告)日：2002-11-19
申请号：US09983294
申请日：2001-10-23
申请人： Kazutami Arimoto , Hiroki Shimano
发明人： Kazutami Arimoto , Hiroki Shimano
IPC分类号： H01L2976
CPC分类号： G11C11/4085 , G11C11/4076 , G11C2207/2281 , H01L27/10805
摘要： In a memory cell contained in a memory circuit portion of a system LSI, a gate electrode of an N-channel MOS transistor and a cell plate electrode of a capacitor are formed by the same interconnection layer. Thus, the system LSI can be produced using the CMOS logic process alone so that the system LSI including the memory circuit portion having a relatively large capacity can be produced at a low cost.
摘要翻译：在包含在系统LSI的存储电路部分的存储单元中，N沟道MOS晶体管的栅电极和电容器的单元板电极由相同的互连层形成。因此，可以仅使用CMOS逻辑处理来制造系统LSI，从而可以以低成本制造包括具有相对大容量的存储器电路部分的系统LSI。

10. 发明授权

US06459113B1 Semiconductor integrated circuit device and method of manufacturing the same, and cell size calculation method for DRAM memory cells 失效
标题翻译：半导体集成电路器件及其制造方法，以及DRAM存储单元的单元尺寸计算方法
公开(公告)号：US06459113B1
公开(公告)日：2002-10-01
申请号：US09760804
申请日：2001-01-17
申请人： Toshinori Morihara , Hiroki Shimano , Kazutami Arimoto
发明人： Toshinori Morihara , Hiroki Shimano , Kazutami Arimoto
IPC分类号： H01L27108
CPC分类号： H01L27/10805 , H01L27/0207
摘要： There is provided a semiconductor integrated circuit device comprising: a field placement creating a field pattern in an array form by closest packing on a first conductance-type semiconductor substrate, the field pattern including a plurality of memory cells which define an active area and a device isolation region of a field effect transistor, and which are arranged in a predetermined pitch in the longitudinal and transverse directions, respectively, each memory cell having a pattern of a certain length-to-width size; a cell plate placement providing a capacitor structure between a second conductance-type diffusion region formed by an impurity implant to the active area and a cell plate electrode formed so as to cover part of the active area with a predetermined cell plate pattern through a capacitor dielectric, the cell plate pattern extending in the transverse direction with a certain length size; and a word line placement in which a word line pattern is arranged in the transverse direction of a vacant zone of the active area in which the cell plate electrode is not formed and serves as a gate electrode of the field effect transistor on the active area, the word line pattern being formed through a gate oxide at a predetermined interval, wherein the layout of a cell array of the memory cells is provided by a closest packing cell configuration.
摘要翻译：提供了一种半导体集成电路器件，包括：场放置，通过在第一导电型半导体衬底上的最密堆积产生阵列形式的场图案，场图案包括限定有源区域的多个存储单元和器件隔离区域，并且分别以纵向和横向方向以预定间距布置，每个存储单元具有一定长度至宽度尺寸的图案; 在通过杂质注入形成的第二电导型扩散区域与有源区域之间提供电容器结构的单元板布置和通过电容器电介质以预定的单元板图案覆盖部分有源区域形成的单元板电极，细胞板图案以一定的长度尺寸在横向上延伸; 以及字线图案，其中在没有形成单元板电极的有源区域的空白区域的横向上布置字线图案，并且用作有源区域上的场效应晶体管的栅电极，所述字线图案是以预定间隔通过栅极氧化物形成的，其中所述存储单元的单元阵列的布局由最接近的封装单元配置提供。

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