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1. 发明授权

US07844938B2 Data correcting hierarchical integrated circuit layout accommodating compensate for long range critical dimension variation 有权
标题翻译：数据校正分层集成电路布局适应补偿长距离临界尺寸变化
公开(公告)号：US07844938B2
公开(公告)日：2010-11-30
申请号：US12109400
申请日：2008-04-25
申请人： Alan E. Rosenbluth , Ian P. Stobert
发明人： Alan E. Rosenbluth , Ian P. Stobert
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： A solution for performing a data correction on a hierarchical integrated circuit layout is provided. A method includes: receiving a CD compensation map for the long range critical dimension variation prior to the data correction; grouping compensation amounts of the CD compensation into multiple compensation ranges; generating multiple target layers corresponding to the multiple compensation ranges; super-imposing a region of the CD compensation map having a compensation amount falling into a compensation range over a respective target layer to generate a target shape; performing the data correction on the layout to generate a data corrected layout; performing the data correction on the target shape separately to generate a data corrected target shape; and combining the data corrected layout and the data corrected target shape based on the CD compensation map.
摘要翻译：提供了一种用于在分层集成电路布局上执行数据校正的解决方案。一种方法包括：在数据校正之前接收用于长距离临界尺寸变化的CD补偿图; 将CD补偿的补偿量分组为多个补偿范围; 产生对应于多个补偿范围的多个目标层; 超级CD补偿图的区域具有落在相应目标层上的补偿范围内的补偿量以产生目标形状; 在布局上执行数据校正以生成数据校正布局; 分别对目标形状进行数据校正，生成数据校正对象形状; 并且基于CD补偿图组合数据校正布局和数据校正目标形状。

2. 发明授权

US08015511B2 Adjustment of mask shapes for improving printability of dense integrated circuit layout 有权
标题翻译：调整面罩形状，提高密集集成电路布局的可印刷性
公开(公告)号：US08015511B2
公开(公告)日：2011-09-06
申请号：US12348331
申请日：2009-01-05
申请人： Azalia Krasnoperova , Ian P Stobert , Klaus Herold
发明人： Azalia Krasnoperova , Ian P Stobert , Klaus Herold
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Embodiments of the present invention provide a method for making mask shape adjustment The method includes creating a first mask shape; identifying one or more mask segments of the first mask shape as candidate mask segments of needing segment adjustment; applying an optical proximity correction (OPC) process to the first mask shape, the OPC process identifying at least one of the candidate mask segments as a constrained mask segment; applying a rotational adjustment to the constrained mask segment; and creating a second mask shape having the constrained mask segment being rotationally adjusted. A system and a machine-readable medium for performing the above method are also provided.
摘要翻译：本发明的实施例提供一种用于制作掩模形状调整的方法。该方法包括产生第一掩模形状; 识别第一掩模形状的一个或多个掩模段作为需要段调整的候选掩码段; 将光学邻近校正（OPC）处理应用于所述第一掩模形状，所述OPC处理将所述候选掩模段中的至少一个识别为约束掩模段; 对受约束的掩模段施加旋转调节; 以及创建具有被约束的掩模段被旋转地调节的第二掩模形状。还提供了用于执行上述方法的系统和机器可读介质。

3. 发明申请

US20090271757A1 DATA CORRECTING HIERARCHICAL INTEGRATED CIRCUIT LAYOUT ACCOMMODATING COMPENSATE FOR LONG RANGE CRITICAL DIMENSION VARIATION 有权
标题翻译：数据校正分层整合电路布局扩展补偿长期关键尺寸变化
公开(公告)号：US20090271757A1
公开(公告)日：2009-10-29
申请号：US12109400
申请日：2008-04-25
申请人： Alan E. Rosenbluth , Ian P. Stobert
发明人： Alan E. Rosenbluth , Ian P. Stobert
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： A solution for performing a data correction on a hierarchical integrated circuit layout is provided. A method includes: receiving a CD compensation map for the long range critical dimension variation prior to the data correction; grouping compensation amounts of the CD compensation into multiple compensation ranges; generating multiple target layers corresponding to the multiple compensation ranges; super-imposing a region of the CD compensation map having a compensation amount falling into a compensation range over a respective target layer to generate a target shape; performing the data correction on the layout to generate a data corrected layout; performing the data correction on the target shape separately to generate a data corrected target shape; and combining the data corrected layout and the data corrected target shape based on the CD compensation map.
摘要翻译：提供了一种用于在分层集成电路布局上执行数据校正的解决方案。一种方法包括：在数据校正之前接收用于长距离临界尺寸变化的CD补偿图; 将CD补偿的补偿量分组为多个补偿范围; 产生对应于多个补偿范围的多个目标层; 超级CD补偿图的区域具有落在相应目标层上的补偿范围内的补偿量以产生目标形状; 在布局上执行数据校正以生成数据校正布局; 分别对目标形状进行数据校正，生成数据校正对象形状; 并且基于CD补偿图组合数据校正布局和数据校正目标形状。

4. 发明申请

US20100175041A1 ADJUSTMENT OF MASK SHAPES FOR IMPROVING PRINTABILITY OF DENSE INTEGRATED CIRCUIT LAYOUT 有权
标题翻译：调整密封形状的改进打印电路集成电路布局的可打印性
公开(公告)号：US20100175041A1
公开(公告)日：2010-07-08
申请号：US12348331
申请日：2009-01-05
申请人： Azalia Krasnoperova , Ian P. Stobert , Klaus Herold
发明人： Azalia Krasnoperova , Ian P. Stobert , Klaus Herold
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Embodiments of the present invention provide a method for making mask shape adjustment The method includes creating a first mask shape; identifying one or more mask segments of the first mask shape as candidate mask segments of needing segment adjustment; applying an optical proximity correction (OPC) process to the first mask shape, the OPC process identifying at least one of the candidate mask segments as a constrained mask segment; applying a rotational adjustment to the constrained mask segment; and creating a second mask shape having the constrained mask segment being rotationally adjusted. A system and a machine-readable medium for performing the above method are also provided.
摘要翻译：本发明的实施例提供一种用于制作掩模形状调整的方法。该方法包括产生第一掩模形状; 识别第一掩模形状的一个或多个掩模段作为需要段调整的候选掩码段; 将光学邻近校正（OPC）处理应用于所述第一掩模形状，所述OPC处理将所述候选掩模段中的至少一个识别为约束掩模段; 对受约束的掩模段施加旋转调节; 以及创建具有被约束的掩模段被旋转地调节的第二掩模形状。还提供了用于执行上述方法的系统和机器可读介质。

5. 发明授权

US08627245B1 Density balancing in multiple patterning lithography using integrated circuit layout fill 有权
标题翻译：使用集成电路布局填充的多重图案化光刻中的密度平衡
公开(公告)号：US08627245B1
公开(公告)日：2014-01-07
申请号：US13596140
申请日：2012-08-28
申请人： Shayak Banerjee , Lars W. Liebmann , Ian P. Stobert
发明人： Shayak Banerjee , Lars W. Liebmann , Ian P. Stobert
IPC分类号： G06F17/50
CPC分类号： G03F7/70466 , G03F7/70433
摘要： In various embodiments, a method of designing an integrated circuit (IC) layout for a multiple patterning layout fill process includes: providing a pre-characterized mask tile library including a plurality of distinct mask tiles each having a distinct mask density on a plurality of distinct exposures each associated with a patterning process in the multiple patterning process; determining a density of a mask group in a first layout window in the IC layout, the first layout window including an open space unfilled by the mask group; and selecting a set of mask tiles from the plurality of distinct mask tiles to fill a portion of the open space, the selecting based upon the determined density of the mask group in the first layout window and the distinct mask density of the selected set of mask tiles on the plurality of distinct exposures.
摘要翻译：在各种实施例中，设计用于多图案化布局填充处理的集成电路（IC）布局的方法包括：提供预先表征的掩模片库，其包括多个不同的掩模片，每个掩模片在多个不同的图案布局填充处理中具有不同的掩模密度在多个图案化工艺中每个与图案化工艺相关联的曝光; 确定所述IC布局中的第一布局窗口中的掩模组的密度，所述第一布局窗口包括未被所述掩模组填充的开放空间; 以及从所述多个不同的掩模块中选择一组掩模块以填充所述开放空间的一部分，所述选择基于所述第一布局窗口中所确定的所述掩模组的密度和所选择的掩模组的所述不同掩模密度多个不同曝光的瓦片。

6. 发明授权

US07380233B2 Method of facilitating integrated circuit design using manufactured property values 有权
标题翻译：使用制造的属性值促进集成电路设计的方法
公开(公告)号：US07380233B2
公开(公告)日：2008-05-27
申请号：US11162196
申请日：2005-08-31
申请人： Jeanne P. Bickford , Steven M. Fox , Donald J. Hathaway , Ian P. Stobert
发明人： Jeanne P. Bickford , Steven M. Fox , Donald J. Hathaway , Ian P. Stobert
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An integrated circuit (IC) design method for use as a design and/or manufacturing tool for designing and/or manufacturing integrated circuitry (110). The method utilizes one or more library element (150A-F) to provide a flexible modeling template. Each library element includes one or more module ports (160A-F) each for accepting any one of a plurality of device modules (170). The device modules are logical representations of corresponding respective portions of the integrated circuitry. For any given module port, the corresponding device modules may be interchanged essentially without additional integrated circuitry design changes.
摘要翻译：一种用作设计和/或制造集成电路（110）的设计和/或制造工具的集成电路（IC）设计方法。该方法利用一个或多个库元素（150A-F）来提供灵活的建模模板。每个库元素包括一个或多个模块端口（160A-F），每个模块端口用于接受多个设备模块（170）中的任何一个。设备模块是集成电路的对应的相应部分的逻辑表示。对于任何给定的模块端口，相应的设备模块可以基本上互换，而没有额外的集成电路设计更改。

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