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1. 发明申请

US20080107168A1 Advanced Digital Receiver 有权
标题翻译：高级数字接收机
公开(公告)号：US20080107168A1
公开(公告)日：2008-05-08
申请号：US11547816
申请日：2005-04-08
申请人： Jingsong Xia , Shidong Chen , Richard W. Citta , Gopalan Krishnamurthy , Scott M. Lopresto , David A. Willming , Xiaojun Yang , Jilian Zhu
发明人： Jingsong Xia , Shidong Chen , Richard W. Citta , Gopalan Krishnamurthy , Scott M. Lopresto , David A. Willming , Xiaojun Yang , Jilian Zhu
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L1/006 , H04L7/0062 , H04L7/042 , H04L25/0212
摘要： A digital receiver for processing a signal received from a channel includes a digital demodulator and an equalizer coupled to the digital demodulator. The equalizer includes a feedforward filter and a decision feedback equalizer (DFE), wherein the feedforward filter includes a plurality of feedforward filter taps. Coefficients are associated with the plurality of feedforward filter taps and the values of all of the coefficients associated with the plurality of feedforward filter taps are dynamically determined.
摘要翻译：用于处理从信道接收的信号的数字接收机包括耦合到数字解调器的数字解调器和均衡器。均衡器包括前馈滤波器和判决反馈均衡器（DFE），其中前馈滤波器包括多个前馈滤波器抽头。系数与多个前馈滤波器抽头相关联，并且动态地确定与多个前馈滤波器抽头相关联的所有系数的值。

2. 发明授权

US07130344B2 Adaptive equalizer having a variable step size influenced by output from a trellis decoder 有权
公开(公告)号：US07130344B2
公开(公告)日：2006-10-31
申请号：US10701047
申请日：2003-11-04
申请人： Jingsong Xia , Richard W. Citta , Scott M. LoPresto , Wenjun Zhang , Hangbin Song
发明人： Jingsong Xia , Richard W. Citta , Scott M. LoPresto , Wenjun Zhang , Hangbin Song
IPC分类号： H03H7/40
CPC分类号： H04L1/006 , H04L1/0054 , H04L1/1671 , H04L25/03057 , H04L2025/0349 , H04L2025/03617 , H04L2025/03624 , H04L2025/03687
摘要： An adaptive equalizer comprises a decision device; a decision feedback equalizer coupled to the decision device; an FIR filter coupled to the decision device; and a trellis decoder coupled to the decision device, adapted to provide a reliability output and a decoded output. An error signal is generated by subtracting an output of the decision feedback equalizer from an output of the decision device, the error signal being used to update coefficients of the taps of the FIR filter and the decision feedback equalizer. A magnitude of the change to the coefficients is selected based at least in part the reliability output of the trellis decoder.

3. 发明授权

US06995617B2 Data-directed frequency-and-phase lock loop 有权
公开(公告)号：US06995617B2
公开(公告)日：2006-02-07
申请号：US10404511
申请日：2003-04-01
申请人： Richard W. Citta , Scott M. LoPresto , Jingsong Xia , Wenjun Zhang
发明人： Richard W. Citta , Scott M. LoPresto , Jingsong Xia , Wenjun Zhang
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/093 , H04L27/38 , H04L2027/0057
摘要： A data-directed frequency-and-phase lock loop for an offset-QAM modulated signal comprises a first multiplier that multiplies the signal by the output of a VCO. The output of the first multiplier is phase-shifted by a second multiplier, then convolved by a third multiplier. The output of the third multiplier is split, with each portion being passed through a frequency-shift multiplier and a frequency-and-phase lock loop. The output of the two frequency-and-phase lock loops is summed and returned to the VCO to complete the feedback loop.

4. 发明授权

US07995648B2 Advanced digital receiver 有权
标题翻译：高级数字接收机
公开(公告)号：US07995648B2
公开(公告)日：2011-08-09
申请号：US11547816
申请日：2005-04-08
申请人： Jingsong Xia , Shidong Chen , Richard W. Citta , Gopalan Krishnamurthy , Scott M. Lopresto , David A. Willming , Xiaojun Yang , Jilian Zhu
发明人： Jingsong Xia , Shidong Chen , Richard W. Citta , Gopalan Krishnamurthy , Scott M. Lopresto , David A. Willming , Xiaojun Yang , Jilian Zhu
IPC分类号： H04B1/10 , H04L1/00
CPC分类号： H04L25/03057 , H04L1/006 , H04L7/0062 , H04L7/042 , H04L25/0212
摘要： A digital receiver for processing a signal received from a channel includes a digital demodulator and an equalizer coupled to the digital demodulator. The equalizer includes a feedforward filter and a decision feedback equalizer (DFE), wherein the feedforward filter includes a plurality of feedforward filter taps. Coefficients are associated with the plurality of feedforward filter taps and the values of all of the coefficients associated with the plurality of feedforward filter taps are dynamically determined.
摘要翻译：用于处理从信道接收的信号的数字接收机包括耦合到数字解调器的数字解调器和均衡器。均衡器包括前馈滤波器和判决反馈均衡器（DFE），其中前馈滤波器包括多个前馈滤波器抽头。系数与多个前馈滤波器抽头相关联，并且动态地确定与多个前馈滤波器抽头相关联的所有系数的值。

5. 发明授权

US07504890B2 Data-directed frequency-and-phase lock loop 有权
标题翻译：数据导向的频相锁相环
公开(公告)号：US07504890B2
公开(公告)日：2009-03-17
申请号：US11318265
申请日：2005-12-23
申请人： Richard W. Citta , Scott M. LoPresto , Jingsong Xia , Wenjun Zhang
发明人： Richard W. Citta , Scott M. LoPresto , Jingsong Xia , Wenjun Zhang
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/093 , H04L27/38 , H04L2027/0057
摘要： A data-directed frequency-and-phase lock loop for an offset-QAM modulated signal comprises a first multiplier that multiplies the signal by the output of a VCO. The output of the first multiplier is phase-shifted by a second multiplier, then convolved by a third multiplier. The output of the third multiplier is split, with each portion being passed through a frequency-shift multiplier and a frequency-and-phase lock loop. The output of the two frequency-and-phase lock loops is summed and returned to the VCO to complete the feedback loop.
摘要翻译：用于偏移QAM调制信号的数据定向的频相锁相环包括将信号乘以VCO的输出的第一乘法器。第一乘法器的输出被第二乘法器相移，然后由第三乘法器卷积。第三乘法器的输出被分离，每个部分通过频移乘法器和频相锁相环。将两个频相锁相环的输出相加并返回到VCO，以完成反馈回路。

6. 发明授权

US07190744B2 Error generation for adaptive equalizer 有权
标题翻译：自适应均衡器产生错误
公开(公告)号：US07190744B2
公开(公告)日：2007-03-13
申请号：US09876547
申请日：2001-06-07
申请人： Jingsong Xia , Richard W. Citta , Scott M. LoPresto , Wenjun Zhang
发明人： Jingsong Xia , Richard W. Citta , Scott M. LoPresto , Wenjun Zhang
IPC分类号： H03D1/00 , H04L27/06
CPC分类号： H04L25/03057 , H04L27/3416 , H04L2025/03382 , H04L2025/0342
摘要： An equalizer comprises: an FIR; a trellis decoder coupled to the FIR; a mapper coupled to the trellis decoder; and a decision feedback equalizer coupled to the mapper. The decision feedback equalizer receives the mapped and scaled output of the trellis decoder as input and an error signal is generated by subtracting an output of the decision feedback equalizer from the input to the trellis decoder.
摘要翻译：均衡器包括：FIR; 耦合到FIR的网格解码器; 耦合到网格解码器的映射器; 以及耦合到映射器的判决反馈均衡器。判决反馈均衡器接收作为输入的网格解码器的映射和缩放输出，并且通过从输入到网格解码器减去判决反馈均衡器的输出来产生错误信号。

7. 发明申请

US20060215748A1 Equalizer for time domain signal processing 审中-公开
公开(公告)号：US20060215748A1
公开(公告)日：2006-09-28
申请号：US11400039
申请日：2006-04-07
申请人： Jingsong Xia , Richard Citta , Scott LoPresto , Wenjun Zhang
发明人： Jingsong Xia , Richard Citta , Scott LoPresto , Wenjun Zhang
IPC分类号： H03H7/30
CPC分类号： H04L25/03057
摘要： A digital equalizer comprises a matched filter that, in conjunction with an FIR filter, assures a single peak with substantially greater energy than other peaks caused by ghosts, thereby permitting synchronization even with multiple, arbitrarily strong ghosts caused by strong multipathing, multiple transmitters, or both.

8. 发明授权

US06904085B1 Multipath ghost eliminating equalizer with optimum noise enhancement 有权
标题翻译：多路径消除均衡器，具有最佳的噪声增强
公开(公告)号：US06904085B1
公开(公告)日：2005-06-07
申请号：US09545447
申请日：2000-04-07
申请人： Richard W. Citta , Scott M. LoPresto , Jingsong Xia
发明人： Richard W. Citta , Scott M. LoPresto , Jingsong Xia
IPC分类号： H04L25/03 , H03H7/30
CPC分类号： H04L25/03159 , H04L2025/03414 , H04L2025/03522 , H04L2025/03617
摘要： An equalizer includes n processing paths arranged to process blocks of data. N−1 data shifters are arranged so that each of the n−1 data shifters is in a corresponding one of the n processing paths and so that one of the n processing path has no data shifter. N finite filters are arranged so that each of the n finite filters is in a corresponding one of the n processing paths, and so that each of the n finite filters applies a corresponding set of finite filter coefficients to the blocks of data. Ghosts of the blocks of data are not eliminated as a result of the application of the sets of finite filter coefficients corresponding to the n finite filters, and n>2. An adder is arranged to add outputs from the n processing paths such that the addition eliminates ghosts of the blocks of data.
摘要翻译：均衡器包括布置成处理数据块的n个处理路径。 n-1个数据移位器被布置成使得n-1个数据移位器中的每一个处于n个处理路径中的相应一个，并且使得n个处理路径中的一个没有数据移位器。 N个有限滤波器被布置成使得n个有限滤波器中的每一个在n个处理路径中的相应一个中，并且使得n个有限滤波器中的每一个向数据块应用相应的一组有限滤波器系数。由于应用与n个有限滤波器相对应的有限滤波器系数集合的结果，并且n> 2，所以不消除数据块的重影。一个加法器被配置成添加来自n个处理路径的输出，使得加法消除数据块的重影。

9. 发明授权

US06725410B2 Interative decoder 有权
标题翻译：迭代解码器
公开(公告)号：US06725410B2
公开(公告)日：2004-04-20
申请号：US09808585
申请日：2001-03-14
申请人： Richard W. Citta , Jingsong Xia
发明人： Richard W. Citta , Jingsong Xia
IPC分类号： H03M1300
CPC分类号： H03M13/2906 , H03M13/134 , H03M13/658
摘要： An iterative decoding system has a first decoder that decodes coded data and a first weighting circuit that reduces channel effects in the coded data based upon a reliability that the first decoder accurately decoded the encoded data. The first weighting circuit produces improved coded data. A second decoder of the iterative decoding system decodes the improved coded data, and a second weighting circuit additionally reduces channel effects in the improved coded data based upon a reliability that the second decoder accurately decoded the improved encoded data.
摘要翻译：迭代解码系统具有解码编码数据的第一解码器和基于第一解码器对编码数据进行精确解码的可靠性降低编码数据中的信道效应的第一加权电路。第一加权电路产生改进的编码数据。迭代解码系统的第二解码器对改进的编码数据进行解码，并且第二加权电路还基于第二解码器对改进的编码数据进行精确解码的可靠性另外减少改进的编码数据中的信道效应。

10. 发明授权

US06650700B1 Dual path ghost eliminating equalizer with optimum noise enhancement 有权
标题翻译：双路幽灵消除均衡器，具有最佳的噪声增强
公开(公告)号：US06650700B1
公开(公告)日：2003-11-18
申请号：US09425522
申请日：1999-10-22
申请人： Richard W. Citta , Scott M. LoPresto , Jingsong Xia
发明人： Richard W. Citta , Scott M. LoPresto , Jingsong Xia
IPC分类号： H03D104
CPC分类号： H04L25/03012 , H04L25/03159 , H04L2025/03522
摘要： A dual path equalizer for processing blocks of data includes first and second pre-processors, first and second finite filters, first and second post-processors, and an adder. The first pre-processor applies coefficients b1 to a received signal, the first finite filter applies coefficients a1 to an output of the first pre-processor in order to substantially eliminate a ghost from the received signal, and the first post-processor applies coefficients c1 to an output of the first finite filter. The second pre-processor applies coefficients b2 to the received signal, the second finite filter applies coefficients a2 to an output of the second pre-processor in order to substantially eliminate a ghost from the received signal, and the second post-processor applies coefficients c2 to an output of the second finite filter. The coefficients b2 are substantially the time reverse of the coefficients b1, the coefficients a2 are substantially the time reverse of the coefficients a1, and the coefficients c2 are substantially the time reverse of the coefficients c1. The adder is arranged to add outputs from the first and second post-processors.
摘要翻译：用于处理数据块的双路径均衡器包括第一和第二预处理器，第一和第二有限滤波器，第一和第二后处理器以及加法器。第一预处理器将系数b1应用于接收信号，第一有限滤波器将系数a1应用于第一预处理器的输出，以便基本上消除来自接收信号的重影，并且第一后处理器应用系数c1 到第一有限滤波器的输出。第二预处理器将系数b2应用于接收信号，第二有限滤波器将系数a2应用于第二预处理器的输出，以便基本上消除来自接收信号的重影，并且第二后处理器应用系数c2 到第二有限滤波器的输出。系数b2基本上是系数b1的时间倒数，系数a2基本上是系数a1的时间倒数，系数c2基本上是系数c1的时间倒数。加法器被布置成添加来自第一和第二后处理器的输出。

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